Integrated circuit component, protected against random logic events, and associated method of manufacture
AssigneeSTMicroelectronics S.r.l.
InventorsFrancois Jacquet, Phillipe Roche, Jean-Pierre Schoellkopf
Life of this patent
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Abstract
A component of an integrated circuit comprises a first capacitor and a second capacitor series-connected between a first node and a second node of the component. This has application to logic circuits and bistable circuits, for example, SRAM type memories, flip-flop trigger circuits, etc.
Claims30
An integrated circuit, comprising:
- a component having a first access node and a second access node;
- a first capacitor having a first node coupled to the first access node and having a second node;
- a second capacitor having a first node coupled to the second access node and having a second node;
- and
- an external voltage-input terminal coupled to the second node of the first capacitor and the second nodes of the first and second capacitors.
The integrated circuit of claim 6, further comprising a second access transistor having a source/drain node coupled to the second access node.
An integrated circuit comprising a component wherein the component comprises a first capacitor and a second capacitor series connected between a first node and a second node of the component.
An integrated circuit comprising a substrate on which several active zones are made, these zones constituting at least one electronic component and comprising a first metal interconnection level forming at least one connection between at least two active zones, wherein the integrated circuit also comprises a first capacitor, a body of an external electrode of this first capacitor extending between the substrate and the first metal interconnection level along an axis substantially perpendicular to the substrate, the external electrode also forming a connection between at least two active zones of the circuit.
A method for making an integrated circuit, during which several appropriate active zones are made to obtain an SRAM type memory cell, wherein the following steps are then performed:
- E1:
- the deposition of a metal layer, to form an external electrode of a first capacitor and to make an interconnection between several active zones,
- E2:
- the deposition of an insulating layer on an inner wall of the external electrode,
- E3:
- the deposition of a metal layer on the insulating layer, to make an internal electrode of the first capacitor.
A method, comprising charging two serially connected capacitors via a common node between the capacitors to reduce the sensitivity of a circuit to a random logic event, the circuit coupled to the capacitors.
A method, comprising charging two serially connected capacitors via a common node between the capacitors to increase the critical charge of a circuit that is coupled to the capacitors.
Dependencies are inferred from the claim text.