Hybrid phase-locked loop
AssigneeRealtek Semiconductor Corp.
InventorHorng-Der Chang
Life of this patent
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AssigneeRealtek Semiconductor Corp.
InventorHorng-Der Chang
Estimating the term…
A hybrid phase-locked loop, comprising: a phase-frequency detector, for detecting the phase difference between a reference signal and an oscillation feedback signal and generating a digital phase-difference signal according to a mean-frequency signal; a digit pump, for receiving the phase-difference signal and generating a proportional gain signal and an accumulative gain signal according to a proportional gain value and an accumulative gain value; a digital filter, for receiving the proportional gain signal and the accumulative gain signal so as to generate a digital control signal; a digit-controlled oscillator (DCO), for receiving the control signal and the mean-frequency signal so as to generate a phase-swap signal; a phase selector, for receiving a plurality of multi-phase signals and the phase-swap signal so as to select one among neighboring phases to be the mean-frequency signal according to the phase-swap signal; an analog phase-locked loop, for receiving the mean-frequency signal and filtering out the cycle-to-cycle jitter thereof so as to generate an output signal; and a frequency divider, for receiving the output signal and dividing the frequency thereof so as to generate the oscillation feedback signal.
A phase-locked loop, comprising:
A method for controlling a hybrid phase-locked loop, comprising steps of:
Dependencies are inferred from the claim text.