US 2003/0117193 A1 · Delay locked loop circuit with improved jitter performance

Abstract

A delay locked loop circuit with a novel structure for improving a jitter performance is disclosed. The delay locked loop circuit includes a delay circuit for receiving an input clock signal and generating a delayed output clock signal. The delay circuit has a predetermined minimum variable delay, and the output clock signal is delayed with respect to the input clock signal by a delay to be determined in accordance with a delay control signal inputted into the delay circuit. Moreover, the delay locked loop circuit includes a phase determining block for receiving the input clock signal and the output clock signal, generating a phase pull signal when a phase of an input clock signal being delayed by a first predetermined time period leads a phase of the output clock signal, and generating a phase push signal when a phase of the input clock signal lags behind a phase of a delayed output clock signal delayed by a second predetermined time, and a delay control circuit for generating the delay control signal for controlling the delay circuit to reduce the delay when the phase pull signal is received from the phase determining block and to increase the delay when the phase push signal is received from the phase determining block. The delay control circuit does not change the delay of the delay circuit when neither the phase pull signal nor the phase push signal is received from the phase determining block.

Claims18

Dependent claims

A delay locked loop circuit with an improved jitter performance, comprising:

a delay circuit for receiving an input clock signal and generating a delayed output clock signal, the delay circuit having a predetermined minimum variable delay, and the delayed output clock signal being delayed with respect to the input clock signal by a delay period to be determined in accordance with a delay control signal which is inputted into the delay circuit;
a phase determining block for receiving the input clock signal and the output clock signal, generating a phase pull signal when a phase of an input clock signal being delayed as much as a first predetermined time period leads a phase of the output clock signal, and generating a phase push signal when a phase of the input clock signal lags behind a phase of an output clock signal being delayed by as much as a second predetermined time;
and
a delay control circuit for generating the delay control signal for controlling the delay circuit to reduce the delay when the phase pull signal is received from the phase determining block and to increase the delay when the phase push signal is received from the phase determining block.

1 more element

A delay locked loop circuit with an improved jitter performance, comprising:

a clock buffer for receiving an external clock signal and generating a buffered input clock signal;
a delay circuit for receiving the input clock signal and generating a delayed output clock signal, the delay circuit having a predetermined minimum variable delay, and the output clock signal being delayed with respect to the input clock signal by a delay period to be determined in accordance with a delay control signal which is inputted into the delay circuit;
a phase determining block for receiving the external clock signal and the output clock signal, generating a phase pull signal when a phase of the external clock signal being delayed by as much as a first predetermined time period leads a phase of the output clock signal, and generating a phase push signal when a phase of the external clock signal lags behind a phase of an output clock signal delayed by as much as a second predetermined time period;
and
a delay control circuit for generating the delay control signal for controlling the delay circuit to reduce the delay when the phase pull signal is received from the phase determining block and to increase the delay when the phase push signal is received from the phase determining block;
wherein the phase determining block includes:
a first delay section for receiving the external clock signal and generating an external clock signal delayed by as much as the first predetermined time period;
a second delay section for receiving the output clock signal and generating an output clock signal delayed by as much as the second predetermined time period;
a first phase determining section for receiving the delayed external clock signal and the output clock signal, and for generating the phase pull signal when the phase of the delayed external clock signal leads the phase of the output clock signal;
and
a second phase determining section for receiving the external clock signal and the delayed output clock signal, and for generating the second phase push signal when the phase of the external clock signal lags behind the phase of the delayed output clock signal.

8 more elements

A delay locked loop circuit with an improved jitter performance, comprising:

a clock buffer for receiving an external clock signal and generating a buffered input clock signal;
a delay circuit for receiving the input clock signal and generating a delayed output clock signal, the delay circuit having a predetermined minimum variable delay, and the output clock signal being delayed with respect to the input clock signal by a delay period to be determined in accordance with a delay control signal which is inputted into the delay circuit;
a phase determining block for receiving the external clock signal and the output clock signal, generating a phase pull signal when a phase of the external clock signal being delayed by as much as a first predetermined time period leads a phase of the output clock signal, and generating a phase push signal when a phase of the external clock signal lags a phase of an output clock signal delayed as much as a second predetermined time period;
and
a delay control circuit for generating the delay control signal for controlling the delay circuit to reduce the delay when the phase pull signal is received from the phase determining block and to increase the delay when the phase push signal is received from the phase determining block;
wherein the phase determining block includes:
a first phase determining section for receiving the delayed external clock signal and the output clock signal, and for generating a first phase pull signal when the phase of the delayed external clock signal leads the phase of the output clock signal, and a first phase push signal when the phase of the delayed external clock signal lags behind the phase of the output clock signal;
a second phase determining section for receiving the external clock signal and the delayed output clock signal, and for generating a second phase pull signal when the phase of the external clock signal leads the phase of the delayed output clock signal, and a second phase push signal when the phase of the external clock signal lags behind the phase of the delayed output clock signal;
a third phase determining section for receiving the external clock signal and the output clock signal, and for generating a third phase pull signal when the phase of the external clock signal leads the phase of the output clock signal, and a third phase push signal when the phase of the external clock signal lags behind the phase of the output clock signal;
a first logic product means for generating the phase pull signal by logically multiplying the first through the third phase pull signals;
and
a second logic product means for generating the phase push signal by logically multiplying the first through the third phase push signals.

9 more elements

Dependencies are inferred from the claim text.

Delay locked loop circuit with improved jitter performance

Life of this patent

Delay locked loop circuit with improved jitter performance

Life of this patent

Abstract

Claims18