Apparatus and method for generating output clock signal having controlled timing

A circuit for generating an output clock signal having controlled timing, comprising:

• an input buffer for generating an input clock signal by receiving and buffering a reference clock signal;
• a first delay circuit which receives the input clock signal to generate a first delayed input clock signal, in which the first delayed input clock signal is an input clock signal delayed by a period determined according to a first delay control signal inputted to the first delayed circuit;
• a second delay circuit which receives the input clock signal to generate a second delayed input clock signal, in which the second delayed input clock signal is an input clock signal delayed by a period determined according to a second delay control signal inputted to the second delayed circuit;
• a phase blending circuit for receiving the first and second delayed input clock signals and blending phases of the first and second delayed input clock signals to generate a phase blended clock signal;
• an output buffer which receives and buffers the phase blended clock signal in order to generate the output clock signal;
• a phase detection circuit which receives the reference clock signal and the output clock signal in order to generate a phase push signal in the case that a phase of the output clock signal is ahead of that of the reference clock signal and to generate a phase pull signal in the case that the phase of the output clock signal is behind that of the reference clock signal;
• and
• a delay control circuit which generates the first or second delay control signal in order to increase the delay when the phase push signal is received from the phase detection circuit and decrease the delay when the phase pull signal is received from the phase detection circuit, in which the first delay control signal and the second delay control signal are not generated simultaneously.

A method for generating a clock signal having controlled timing, the method comprising the steps of:

• generating a first delayed input clock signal, by delaying an input clock signal by a period determined according to a first delay control signal, after receiving the input clock signal and the first delay control signal;
• generating a second delayed input clock signal, by delaying an input clock signal by a period determined according to a second delay control signal, after receiving the input clock signal and the second delay control signal;
• generating a phase blended clock signal by receiving the first and second delayed input clock signals and blending phases of the first and second delayed input clock signals;
• after receiving a reference clock signal and the phase blended clock signal, generating a phase push signal in the case that a phase of the phase blended clock signal is ahead of that of the reference clock signal and generating a phase pull signal in the case that the phase of the phase blended clock signal is behind that of the reference clock signal;
• and
• generating a first or second delay control signal for increasing the delay when the phase push signal is generated and for decreasing the delay when the phase pull signal is generated.