Clock synchronization circuit
AssigneeHynix Semiconductor Inc.
InventorJong Tae Kwak
Life of this patent
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Abstract
A clock synchronization circuit using a phase mixer is disclosed. The clock synchronization circuit generates an internal clock signal having a phase between phases of two clock signals generated in two variable delay lines with a predetermined phase difference by using the phase mixer, thereby precisely synchronizing the clock signal. When a shift register for controlling the variable delay line performs a shift operation, the output clock signal from the variable delay line where the shift operation is performed is not inputted to the phase mixer, but the output clock signal from the other variable delay line is inputted to the phase mixer. As a result, jitter elements generated due to the shift operation do not influence the internal clock signal.
Claims10
A clock synchronization circuit comprising:
- at least two variable delay lines for respectively delaying an external clock signal for a different delay time;
- at least two shift registers for respectively controlling the delay time of the variable delay lines;
- a phase mixer for mixing phases of the clock signals delayed by the variable delay units, and outputting an internal clock signal having a phase between phases of the delayed clock signals;
- a phase detecting unit for comparing the phase of the external clock signal with the phase of the internal clock signal, and outputting a plurality of control signals for controlling the respective shift registers;
- and
- a control unit for outputting a first control signal for determining the phase of the internal clock signal by controlling the phase mixer, and a second control signal for controlling at least one shift register of the shift registers to perform a shift operation according to the plurality of control signals from the phase detecting unit.
A clock synchronization circuit for respectively synchronizing an internal clock signal and an inverted internal clock signal with an external clock signal and an inverted external clock signal having the opposite phase to the external clock signal, the clock synchronization circuit, comprising:
- a normal internal clock signal generator for generating a normal internal clock signal by using at least two first variable delay lines for delaying the external clock signal, and mixing phases of clock signals outputted by the first variable delay lines;
- and
- an inverted internal clock signal generator for generating the inverted internal clock signal having the opposite phase to the internal clock signal, by using at least two second variable delay lines for delaying the inverted external clock signal having the opposite phase to the external clock signal, and mixing phases of clock signals outputted by the second variable delay lines.
Dependencies are inferred from the claim text.