US 2003/0117190 A1 · PLL circuit

Abstract

VDLs I1 and 1R delay an input clock ICLK and a return clock RCLK and provide a delayed input clock DICLK and a delayed return clock DRCL to a PLL part 10. The PLL part 10 receives the delayed input clock DICLK and the delayed return clock DRCLK, and outputs a PLL output OUTP so that these signals are synchronous with each other. This PLL output OUTP finally returns as a return clock RCLK via an external circuit. A PD 3 detects a phase difference between the input clock ICLK and the return clock RCLK, and outputs a phase comparison signal SPD. A control logic circuit 2 determines a degree of phase advance of the return clock RCLK with respect to the input clock ICLK based on the phase comparison signal SPD, and controls a delay time DT of the VDL 1R so that a phase error between the input clock ICLK and the return clock RCLK is zero.

Claims15

Dependent claims

A PLL circuit comprising:

first delay means for delaying a reference clock by a first delay time to obtain a delayed reference clock;
second delay means for delaying a return clock by a second delay time to obtain a delayed return clock;
a PLL part for receiving said delayed reference clock and said delayed return clock and outputting a PLL output so that phases of these clocks are synchronous with each other, a signal in association with said PLL output being returned as said return clock;
and
phase difference reducing delay control means for performing a delay means controlling process based on said reference clock and said return clock, said delay means control process changing at least one of said first and second delay times so that a phase difference between said reference clock and said return clock is reduced.

2 more elements

Dependencies are inferred from the claim text.

PLL circuit

Life of this patent

PLL circuit

Life of this patent

Abstract

Claims15