Semiconductor device having internal circuit operating in synchronization with internal clock signal
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorJingo Nakanishi
Life of this patent
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Abstract
A semiconductor integrated circuit chip includes a replica circuit for delaying a reference clock signal, a delay detector for controlling a delay time of the replica circuit such that the delay time of replica circuit becomes one-fourth the period of the reference clock signal, and an EX-OR gate that receives the reference clock signal and an output clock signal from replica circuit for supplying to a logic circuit an internal clock signal that is obtained by multiplying the reference clock signal by two. Thus, the consumed power can be kept small in comparison with the conventional example in which an internal clock signal is propagated on a clock line.
Claims20
A semiconductor device, comprising:
- an internal circuit that operates in synchronization with an internal clock signal;
- a first delay circuit having a first delay time that is controlled by a control signal for delaying a reference clock signal;
- a second delay circuit having a second delay time that is controlled by said control signal and that is derived by multiplying said first delay time by a first proportionality constant for delaying said reference clock signal;
- a phase control circuit for comparing phases of said reference clock signal and an output clock signal from said first delay circuit to generate and supply to said first and second delay circuits said control signal such that a phase difference thereof becomes a predetermined value;
- and
- an internal clock generating circuit for generating and supplying to said internal circuit said internal clock signal obtained by multiplying said reference clock signal based on said reference clock signal and an output clock signal from said second delay circuit.
A semiconductor device, comprising:
- an internal circuit that operates in synchronization with an internal clock signal;
- a frequency divider for dividing an external clock signal to generate a reference clock signal;
- a first delay circuit having a first delay time that is controlled by a control signal for delaying said external clock signal;
- a second delay circuit having a second delay time that is controlled by said control signal and that is derived by multiplying said first delay time by a predetermined proportionality constant for delaying said reference clock signal;
- a phase control circuit for comparing phases of said external clock signal and an output clock signal from said first delay circuit to generate and supply to said first and second delay circuits said control signal such that a phase difference thereof becomes a predetermined value;
- and
- an internal clock generating circuit for generating and supplying to said internal circuit said internal clock signal obtained by multiplying said reference clock signal based on said reference clock signal and an output clock signal from said second delay circuit.
A semiconductor device, comprising:
- an internal circuit that operates in synchronization with an internal clock signal;
- a ring oscillator for generating a first clock signal having a period controlled by a control signal;
- a delay circuit having a delay time that is controlled by said control signal and that is derived by multiplying the period of said first clock signal by a predetermined proportionality constant for delaying said first clock signal;
- a frequency divider for dividing said first clock signal to generate a second clock signal;
- a phase control circuit for comparing phases of a reference clock signal and said second clock signal and generating and supplying to said ring oscillator and said delay circuit said control signal such that a phase difference thereof becomes a predetermined value;
- and
- an internal clock generating circuit for generating and supplying to said internal circuit said internal clock signal that is obtained by multiplying said reference clock signal based on said first clock signal and an output clock signal from said delay circuit.
Dependencies are inferred from the claim text.