Back to results
US 2003/0117187 A1Published application
Frequency dividing circuit
AssigneeBroadcom Corporation
InventorsKa Lun Choi, Derek Hing Sang Tam
Life of this patent
Estimating the term…
Abstract
A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency of the master clock signal divided by that non-integer factor. In one embodiment, the circuit is operative to divide the master clock frequency by 2.5.
Claims15
A dividing circuit comprising:
- a first group of bistable devices, each device being configured to produce a first output signal in response to a received master clock signal;
- and
- a plurality of circuit stages, each stage including at least one bistable device from a second group of bistable devices and being coupled, at least indirectly, to one or more output ports of the devices of the first group, the plurality of stages being configured to produce a second output signal;
- wherein each stage is configured to receive as an input a respective slaved clock signal, each respective slaved clock signal having characteristics different from characteristics of the master clock signal;
- and
- wherein the second output signal has a frequency substantially equal to a frequency of the master clock signal divided by a non-integer factor.
3 more elements
A dividing circuit comprising:
- a first circuit portion including a synchronous counter configured to receive a first clock signal as an input and produce an output signal in response thereto;
- and
- at least a second circuit portion including a plurality of circuit stages, each stage being configured to receive a respective clock signal, each respective clock signal having characteristics different from the first clock signal, the second circuit portion (i) being electrically connected to the first circuit portion, (ii) being configured to receive the output signal therefrom, and (iii) produce an output clock signal having a frequency numerically related to a frequency of the first clock signal.
A method to generate a frequency divided output clock signal comprising:
- receiving a first clock signal;
- shifting a phase of the first clock signal to produce a plurality of phase shifted clock signals;
- and
- producing a frequency divided output clock signal based upon the first clock signal and the plurality of phase shifted clock signals.
1 more element
A dividing circuit comprising:
- means for producing a first output signal in response to a received master clock signal;
- and
- means for producing a second output signal coupled to the means for producing a first output signal;
- wherein the means for producing a second output signal is configured to receive as an input one or more slaved clock signals, each having characteristics different from characteristics of the master clock signal;
- and
- wherein the means for producing a second output signal is configured to produce a second output signal having a frequency substantially equal to a frequency of the master clock signal divided by a non-integer factor.
3 more elements
An apparatus for generating a frequency divided output clock signal comprising:
- means for receiving a first clock signal;
- means for shifting a phase of the first clock signal to produce a plurality of phase shifted clock signals;
- and
- means for producing a frequency divided output clock signal based upon the first clock signal and the plurality of phase shifted clock signals.
1 more element
Dependencies are inferred from the claim text.