Back to results
US 2003/0117186 A1Published application
Conditional clock buffer circuit
AssigneeBroadcom Corporation
InventorDaniel W. Dobberpuhl
Life of this patent
Estimating the term…
Abstract
A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.
Claims10
A clock buffer circuit comprising:
- a precharge circuit configured to precharge a first node and a second node;
- a first transistor having a first terminal coupled to the first node, a second terminal, and a first control terminal coupled to receive a condition signal;
- a second transistor having a third terminal coupled to the second node, a fourth terminal coupled to the second terminal, and a second control terminal coupled to the first node;
- and
- a third transistor having a fifth terminal coupled to the second terminal and the fourth terminal, a sixth terminal, and a third control terminal coupled to receive a clock signal;
- wherein the first terminal is activated responsive to the condition signal, and wherein the second transistor is prevented from discharging the second node responsive to the first transistor being activated, the second node representing an output clock signal from the clock buffer circuit.
3 more elements
An integrated circuit comprising:
- a functional logic unit;
- a conditional logic unit coupled to the functional logic unit, the conditional logic unit configured to produce a condition signal;
- and
- a conditional clock buffer circuit coupled to the conditional logic unit and configure to drive an output clock signal to the functional logic unit, the conditional clock buffer circuit comprising:
- a precharge circuit configured to precharge a first node and a second node;
- a first transistor having a first terminal coupled to the first node, a second terminal, and a first control terminal coupled to receive a condition signal;
- a second transistor having a third terminal coupled to the second node, a fourth terminal coupled to the second terminal, and a second control terminal coupled to the first node;
- and
- a third transistor having a fifth terminal coupled to the second terminal and the fourth terminal, a sixth terminal, and a third control terminal coupled to receive a clock signal;
- wherein the first transistor is activated responsive to the condition signal, and wherein the second transistor is prevented from discharging the second node responsive to the first transistor being activated, the second node representing an output clock signal from the clock buffer circuit.
7 more elements
Dependencies are inferred from the claim text.