Circuit device
AssigneeSemiconductor Technology Academic Research Center
InventorsKoichiro Ishibashi, Takahiro Yamashita, Yukio Arima
Life of this patent
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Abstract
A circuit device comprising a bus including a plurality of wires, and a plurality of driving circuits which output input data to the wires in synchronism with a reference signal, each of the driving circuits being configured to have a first delay time of an output signal from the reference signal when a logic value of an input signal transits from “0” to “1” and a second delay time of the output signal from the reference signal when the logic value of the input signal transits from “1” to “0”, the first and second delay times being different from each other.
Claims4
A circuit device comprising:
- a bus including a plurality of wires;
- and
- a plurality of driving circuits which output input data to the wires in synchronism with a reference signal,
- each of the driving circuits being configured to have a first delay time of an output signal from the reference signal when a logic value of an input signal transits from “0” to “1” and a second delay time of the output signal from the reference signal when the logic value of the input signal transits from “1” to “0”, the first and second delay times being different from each other.
Dependencies are inferred from the claim text.