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US 2003/0117182 A1Published application
Sense amplifier and electronic apparatus using the same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsYutaka Shionoiri, Kiyoshi Kato, Munehiro Azami
Life of this patent
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Abstract
A sense amplifier according to the present invention for detecting a potential difference of signals input to a first input terminal and a second input terminal, includes a first means for applying voltages corresponding to threshold voltages of first and second transistors to gate-source voltages of the first and second transistors, and a second means for transferring signals input to the first and second input terminals to gates of the first and second transistors. In this case, a threshold variation of the first and second transistors is corrected.
Claims76
A sense amplifier for detecting a potential difference between signals input to a first input terminal and a second input terminal, comprising:
- first means for applying voltages corresponding to threshold values of first and second transistors to gate-source voltages of the first and the second transistors, respectively;
- and
- second means for transferring signals input to the first and the second input terminals to gates of the first and the second transistors,
- wherein a threshold variation in the first and second transistors is corrected.
1 more element
A sense amplifier for detecting a potential difference of signals input to a first input terminal and a second input terminal, comprising:
- a first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth switches;
- a first, second, third, and fourth capacitor, wherein a second terminal of the first capacitor is electrically connected to a first terminal of the sixth switch and a first terminal of the seventh switch, and a second terminal of the second capacitor is electrically connected to a first terminal of the eighth switch and a first terminal of the ninth switch;
- a first, second, and third power source;
- a first PMOS transistor comprising a source electrically connected to the first power source, a drain electrically connected to a first terminal of the first switch, and a gate electrically connected to the drain;
- a second PMOS transistor comprising a source electrically connected to the first power source, a drain electrically connected to a first terminal of the second switch, and a gate electrically connected to the drain of the first PMOS transistor;
- a first NMOS transistor comprising a gate electrically connected to a second terminal of the third switch, a first terminal of the first capacitor, and a first terminal of the second capacitor;
- a second NOMS transistor comprising a gate electrically connected to a second terminal of the fourth switch, a first terminal of the third capacitor and a first terminal of the fourth capacitor, wherein both sources of the first and second NMOS transistors are electrically connected to a first terminal of the fifth switch, a second terminal of the second capacitor and a second terminal of the fourth capacitor;
- and
- an output terminal electrically connected to the drain of the second PMOS transistor,
- wherein a second terminal of the first switch is electrically connected to a drain of a first NMOS transistor and a first terminal of the third switch, and a second terminal of the second switch is electrically connected to a drain of the second NMOS transistor and a first terminal of the fourth switch, and
- wherein a second terminal of the fifth switch is electrically connected to the second power source, a second terminal of the sixth switch is electrically connected to the first input terminal, a second terminal of the seventh switch is electrically connected to the third power source, a second terminal of the eighth switch is electrically connected to the second input terminal, and a second terminal of the ninth switch is electrically connected to the third power source.
8 more elements
A sense amplifier for detecting a potential difference of signals input to a first input terminal and a second input terminal, comprising:
- a first, second, and third power source;
- a first, second, third, fourth, and fifth switches, wherein a second terminal of the fifth switch is electrically connected to the second power source;
- a first, second, third, and fourth capacitor, wherein a second terminal of the first capacitor is electrically connected to the first input terminal, and a second terminal of the second capacitor is electrically connected to the second input terminal;
- a first PMOS transistor comprising a source electrically connected to the first power source, a drain electrically connected to a first terminal of the first switch, and a gate electrically connected to the drain;
- a second PMOS transistor comprising a source electrically connected to the first power source, a drain electrically connected to a first terminal of the second switch, and a gate electrically connected to the drain of the first PMOS transistor;
- a first NMOS transistor comprising a gate electrically connected to a second terminal of the third switch, a first terminal of the first capacitor, and a first terminal of the second capacitor;
- a second NOMS transistor comprising a gate electrically connected to a second terminal of the fourth switch, a first terminal of the third capacitor and a first terminal of the fourth capacitor, wherein both sources of the first and second NMOS transistors are electrically connected to a first terminal of the fifth switch, a second terminal of the second capacitor and a second terminal of the fourth capacitor;
- and
- an output terminal electrically connected to a drain of the second PMOS transistor.
6 more elements
A sense amplifier for detecting a potential difference of signals input to a first input terminal and a second input terminal, comprising:
- a first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth switches;
- a first, second, third, and fourth capacitor, wherein a second terminal of the first capacitor is electrically connected to a first terminal of the sixth switch and a first terminal of the seventh switch, and a second terminal of the second capacitor is electrically connected to a first terminal of the eighth switch and a first terminal of the ninth switch;
- a first, second, third power source;
- a first resistor having a first terminal electrically connected to the first power source and a second terminal electrically connected to a first terminal of the first switch;
- a second resistor having a first terminal electrically connected to the first power source and a second terminal electrically connected to a first terminal of the second switch;
- a first NNOS transistor, wherein a gate of the first NMOS transistor is electrically connected to a second terminal of the third switch, a first terminal of the first capacitor and a first terminal of the second capacitor;
- a second NMOS transistor, wherein a gate of the second NMOS transistor is electrically connected to a second terminal of the fourth switch, a first terminal of the third capacitor and a first terminal of the fourth capacitor, and both sources of the first and second NMOS transistors are electrically connected to a first terminal of the fifth switch, a second terminal of the second capacitor and a second terminal of the fourth capacitor;
- and
- an output terminal electrically connected to a drain of the second resistor,
- wherein a second terminal of the first switch is electrically connected to a drain of the first NMOS transistor and a first terminal of the third switch, a second terminal of the second switch is electrically connected to a drain of a drain of the second NMOS transistor and a first terminal of the fourth switch, and
- wherein a second terminal of the fifth switch is electrically connected to the second power source, a second terminal of the first capacitor is electrically connected to a first terminal of the sixth switch and a first terminal of the seventh switch, a second terminal of the second capacitor is electrically connected to a first terminal of the eighth switch and a first terminal of the ninth switch, a second terminal of the sixth switch is electrically connected to the first input terminal, a second terminal of the seventh switch is electrically connected to the third power source, a second terminal of the eighth switch is electrically connected to the second input terminal, and a second terminal of the ninth switch is electrically connected to the third power source.
8 more elements
A sense amplifier for detecting a potential difference of signals input to a first input terminal and a second input terminal, comprising:
- a first, second, third, fourth, and fifth switches;
- a first, second, third, and fourth capacitor, wherein a second terminal of the first capacitor is electrically connected to the first input terminal, and a second terminal of the second capacitor is electrically connected to the second input terminal;
- a first, second, third power source;
- a first resistor having a first terminal electrically connected to the first power source and a second terminal electrically connected to a first terminal of the first switch;
- a second resistor having a first terminal electrically connected to the first power source and a second terminal electrically connected to a first terminal of the second switch;
- a first NNOS transistor, wherein a gate of the first NMOS transistor is electrically connected to a second terminal of the third switch, a first terminal of the first capacitor and a first terminal of the second capacitor;
- a second NMOS transistor, wherein a gate of the second NMOS transistor is electrically connected to a second terminal of the fourth switch, a first terminal of the third capacitor and a first terminal of the fourth capacitor, and both sources of the first and second NMOS transistors are electrically connected to a first terminal of the fifth switch, a second terminal of the second capacitor and a second terminal of the fourth capacitor;
- and
- an output terminal electrically connected to a drain of the second resistor.
6 more elements
A sense amplifier for detecting a potential difference of signals input to a first input terminal and a second input terminal, comprising:
- a first, second, and third power sources;
- a first, second, third, fourth fifth, sixth, seventh, eighth, and ninth switches, wherein both first terminals of the first and second switches are electrically connected to the first power source;
- a first, second, third, and fourth capacitor, wherein a second terminal of the first capacitor is electrically connected to a first terminal of the sixth switch and a first terminal of the seventh switch, and a second terminal of the second capacitor is electrically connected to a first terminal of the eighth switch and a first terminal of the ninth switch;
- a first NMOS transistor, wherein a gate of the first NMOS transistor is electrically connected to a second terminal of the third switch, a first terminal of the first capacitor and a first terminal of the second capacitor;
- the second NMOS transistor, wherein a gate of the second NMOS transistor is electrically connected to a second terminal of the fourth switch, a first terminal of the third capacitor and a first terminal of the fourth capacitor, and both sources of the first and second NMOS transistors are electrically connected to a first terminal of the fifth switch, a second terminal of the second capacitor and a second terminal of the fourth capacitor;
- and
- an output terminal electrically connected to a second terminal of the second switch,
- wherein a second terminal of the first switch is electrically connected to a drain of the first NMOS transistor and a first terminal of the third switch, and a second terminal of the second switch is electrically connected to a drain of the second NMOS transistor and a first terminal of the fourth switch, and
- wherein a second terminal of the fifth switch is electrically connected to the second power source, a second terminal of the sixth switch is electrically connected to a first input terminal, a second terminal of the seventh switch is electrically connected to a third power source, a second terminal of the eighth switch is electrically connected to the second input terminal, and a second terminal of the ninth switch is electrically connected to a third power source.
6 more elements
A sense amplifier for detecting a potential difference of signals input to a first input terminal and a second input terminal, comprising:
- a first, second, and third power sources;
- a first, second, third, fourth fifth, sixth, seventh, eighth, and ninth switches, wherein both first terminals of the first and second switches are electrically connected to the first power source, and a second terminal of the fifth switch is electrically connected to the second power source;
- a first, second, third, and fourth capacitor, wherein a second terminal of the first capacitor is electrically connected to the first input terminal, and a second terminal of the second capacitor is electrically connected to the second input terminal;
- a first NMOS transistor, wherein a gate of the first NMOS transistor is electrically connected to a second terminal of the third switch, a first terminal of the first capacitor and a first terminal of the second capacitor;
- the second NMOS transistor, wherein a gate of the second NMOS transistor is electrically connected to a second terminal of the fourth switch, a first terminal of the third capacitor and a first terminal of the fourth capacitor, and both sources of the first and second NMOS transistors are electrically connected to a first terminal of the fifth switch, a second terminal of the second capacitor and a second terminal of the fourth capacitor;
- and
- an output terminal electrically connected to a second terminal of the second switch,
- wherein a second terminal of the first switch is electrically connected to a drain of the first NMOS transistor and a first terminal of the third switch, and a second terminal of the second switch is electrically connected to a drain of the second NMOS transistor and a first terminal of the fourth switch.
5 more elements
A sense amplifier comprising:
- a first transistor having a gate connected to a first input terminal;
- a second transistor having a gate connected to a second input terminal;
- a third transistor having a source connected to a first power source;
- a fourth transistor having a source connected to the first power source;
- and
- first means for causing gate-source voltages of the third and fourth transistors to store voltage corresponding to threshold values of the third and fourth transistors,
- wherein sources of the first and second transistors are connected to each other;
- and
- wherein a threshold variation of the first and second transistors is corrected.
6 more elements
A sense amplifier for detecting a potential difference of signals input to a first input terminal and a second input terminal, comprising:
- a first and second power sources;
- a first, second, and third switches wherein a second terminal of the third switch is connected to the second power source;
- a first and second capacitors;
- a first PMOS transistor, wherein a gate of the first PMOS transistor is connected to a second terminal of the first switch and a second terminal of the first capacitor;
- a second PMOS transistor, wherein a gate of the second PMOS transistor is connected to a second terminal of the second switch and a second terminal of the second capacitor, and both sources of the first and the second PMOS transistors are connected to the first power source;
- a first NMOS transistor, wherein a gate of a gate of the first NMOS transistor is connected to the first input terminal, and a drain of the first NMOS transistor is connected to a drain of the first PMOS transistor, a first terminal of the first switch, a first terminal of the first capacitor, and a first terminal of the second capacitor;
- a second NMOS transistor the second input terminal connected to a gate of a second NMOS transistor;
- the second NMOS transistor having a drain connected to a drain of a second PMOS transistor and a first terminal of a second switch;
- the first NMOS transistor and the second NMOS transistor both having sources connected to a first terminal of a third switch;
- an output terminal connected to a drain of the second NMOS transistor.
7 more elements
A sense amplifier for detecting a potential difference of signals input to a first input terminal and a second input terminal, comprising:
- a first and second power sources;
- a first, second, third, and fourth switches, wherein the first switch has a first terminal connected to a first terminal of a third switch, and the second switch has a first terminal connected to a first terminal of a fourth switch;
- a first and second capacitors
- a first PMOS transistor, wherein a drain of the first PMOS transistor is connected to a first terminal of the first switch, a first terminal of the first capacitor;
- and a first terminal of the second capacitor, and a gate of the first PMOS transistor is connected to a second terminal of the first switch and a second terminal of the first capacitor;
- a second PMOS transistor, wherein a drain of the second PMOS transistor is connected to a first terminal of the second switch, a gate of the second PMOS transistor is connected to a second terminal of the second switch and a second terminal of the second capacitor, and both sources of the first second PMOS transistors are connected to the first power source;
- a first NMOS transistor, wherein a gate of the first NMOS transistor is connected to the first input terminal, wherein a drain of the first NMOS transistor is connected to a second terminal of the third switch;
- a second NMOS transistor, wherein a gate of the second NMOS transistor is connected to the second input terminal, wherein a drain of the second NMOS transistor is connected to a second terminal of the fourth switch;
- a third NMOS transistor, wherein a source of the third NMOS transistor is connected to a second power source;
- and
- an output terminal connected to a drain of the second NMOS transistor,
- wherein both sources of the first and second NMOS transistors are connected to a drain of the third NMOS transistor;
9 more elements
A sense amplifier for detecting a potential difference of signals input to a first input terminal and a second input terminal, comprising:
- a first, second, and third sources;
- a first, second, third, fourth, fifth, and sixth switches, wherein a first terminal of the first switch is connected to a first terminal of the third switch, a first terminal of the second switch is connected to a first terminal of the fourth switch, and both second terminals of the fifth and sixth switches are connected to the third power source;
- a first and second capacitor;
- a first PMOS transistor, wherein a drain of the first PMOS transistor is connected to a first terminal of the first switch, a first terminal of the first capacitor and a first terminal of the second capacitor, and a gate of the first PMOS transistor is connected to a second terminal of the first switch and a second terminal of the first capacitor;
- a second PMOS transistor, wherein a drain of the second PMOS transistor is connected to a first terminal of the second switch, and both sources of the first and second PMOS transistor are connected to the first power source, and a gate of the second PMOS transistor is connected to a second terminal of the second switch and a second terminal of the second capacitor;
- a first NMOS transistor, wherein a drain of the first NMOS transistor is connected to a second terminal of the third switch, and a gate of the first NMOS transistor is connected to the first input terminal, wherein a gate of a second NMOS transistor is connected to the second input terminal;
- a second NMOS transistor, wherein a drain of the second NMOS transistor is connected to a second terminal of the fourth switch;
- a third NMOS transistor, wherein a source of the third NMOS transistor is connected to the second power source,
- an output terminal connected to a drain of the second NMOS transistor.
- wherein both sources of the first and second NMOS transistors are connected to a drain of the third NMOS transistor, and
- wherein a drain of the first PMOS transistor is connected to a first terminal of the fifth switch, and a drain of the second PMOS transistor is connected to a first terminal of the sixth switch.
8 more elements
Dependencies are inferred from the claim text.