Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation
AssigneeIntel Corporation
InventorsSteven K. Hsu, Ram Krishnamurthy
Life of this patent
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Abstract
An embodiment zipper circuit achieves reduced leakage current by utilizing four voltages so that FETs in the p-logic blocks and n-logic blocks are reversed biased during a pre-charge phase. The FETs in a logic block are also reversed biased during an evaluation phase if the input voltages to the logic block are such that the logic block is not driven ON during the evaluation phase.
Claims22
A domino circuit comprising:
- a second stage comprising a n-logic block, the n-logic block comprising a nMOSFET having a gate and a source;
- and
- a first stage to drive the nMOSFET ON and OFF;
- wherein the first stage drives the nMOSFET into a reverse-biased state when driving the nMOSFET OFF.
A circuit comprising:
- a first rail;
- a second rail;
- and
- a domino circuit having a pre-charge phase and an evaluation phase and comprising a second stage, the second stage comprising:
- a node;
- a n-logic block comprising a set of input ports, each input port having a voltage, the n-logic block to conditionally provide a low impedance path between the node and the second rail during the evaluation phase depending upon the set of input port voltages;
- the domino circuit further comprising a first stage, the first stage comprising
- a node connected to an input port belonging to the set of input ports;
- and
- a pulldown to provide a low impedance path between the node and the first rail during the pre-charge phase.
A method to reduce leakage current in a domino zipper circuit having a pre-charge phase and an evaluation phase, the domino zipper circuit comprising a n-logic block having at least one input voltage and a p-logic block having at least one input voltage, the method comprising:
- pulling a first node to a first voltage during the pre-charge phase, wherein the p-logic block conditionally pulls the first node to a third voltage during the evaluation phase depending upon the at least one input voltage to the p-logic block;
- and
- pulling a second node to a fourth voltage during the pre-charge phase, wherein the n-logic block conditionally pulls the second node to a second voltage during the evaluation phase depending upon the at least one input voltage to the n-logic block;
- wherein the fourth voltage is greater than the third voltage, the third voltage is greater than the second voltage, and the second voltage is greater than the first voltage.
Dependencies are inferred from the claim text.