Generic serial port architecture and system
AssigneeAnalog Devices, Inc.
InventorsJean-Louis Tardieux, Joern Soerensen
Life of this patent
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Abstract
A high-speed programmable serial port having a finite state machine, a clock generator capable of controlling shifting of bits from a shift register and a shift register having a bit counter capable of maintaining a numbered count of data bits in a serial output. The clock generator and shift register reduce the burdens on a finite state machine, thus improving data throughput and the ability to provided data according to a multitude of data protocols.
Claims40
For use in a programmable serial port having a first shift register module and a finite state machine, a clock generator comprising:
- a first output channel to a first shift register module, the first output channel providing to the first shift register a first clock signal comprising a predetermined number of pulses, at a predetermined rate in response to at least one instruction determining said number of pulses and said rate, and
- an input channel to receive at least one instruction, the at least one instruction indicative of the predetermined number of pulses, and the predetermined rate.
A shift register control module, to control a first shift register module including a first shift register having an input channel to receive a parallel input of a first plurality of bits and a serial output channel to provide a serial output of a second plurality of bits, and further having at least one register for controlling the shift register responsive to instructions, comprising:
- a first finite state machine to provide said instructions;
- and
- a clock generator coupled to the first finite state machine, providing a first clock signal comprising a first plurality of clock pulses to the first shift register in response to at least one instruction from the first finite state machine, the serial output of the second plurality of bits occurring in response to at least one of said instructions provided to the first shift register module and the first clock signal.
A programmable serial port, comprising:
- a first shift register module including a shift register having an input channel to receive a parallel input of a first plurality of bits and a first output channel to provide a serial output of a second plurality of bits, and further having a register for controlling the shift register module responsive to instructions;
- a first finite state machine to provide said instructions, the finite state machine providing said instructions to the shift register module to control operation of the shift register;
- and
- a clock generator coupled to the finite state machine, providing a first clock signal comprising a first plurality of clock pulses to the first shift register module in response to at least one of said instructions from the finite state machine, the serial output of the second plurality of bits occurring in response to said instructions provided to the shift register module and the first clock signal.
A programmable serial port, comprising:
- a shift register module having an input channel to receive a parallel input of a plurality of bits and an output channel to provide a serial output of the plurality of bits, the shift register module including a shift register to provide the serial output and a bit counter, the bit counter configured to maintain a numbered count of the serial output of the plurality of bits, the serial output and the bit counter responsive to instructions;
- and
- a finite state machine coupled to the shift register module to provide said instructions to the shift register module.
A method of controlling a shift register module comprising a first shift register containing a first plurality of bits, to provide a serial output according to a selected one of a plurality of serial communications protocols, the first shift register module coupled to a clock generator and a finite state machine, said method comprising:
- according to the selected protocol, selecting an instruction sequence to be executed by the finite state machine from among a plurality of instruction sequences, each of the instruction sequences corresponding to a protocol;
- controlling the clock generator according to an instruction of the selected instruction sequence to provide a first plurality of clock pulses to the shift register module, without further control by the finite state machine;
- and
- outputting a second plurality of bits corresponding to first plurality of bits in response to the clock pulses and execution of the instruction sequence.
Dependencies are inferred from the claim text.