System and method for improving signal propagation

A method for sending a data signal over a first segment and a second segment of an integrated circuit (IC) transmission line, comprising:

• transmitting a control signal having a cycle with a predetermined active portion and a predetermined inactive portion;
• during the active portion of the control signal, powering up at least one driving circuit, and driving a first signal on the first segment and an inverted first signal on the second segment using the driving circuits;
• and
• during an inactive portion of the control signal, isolating the first segment and the second segment, electrically connecting the first segment to the second segment to share a charge between the first segment and the second segment, and powering down at least a portion of the driving circuit.

A method for sending a data signal over an integrated circuit (IC) transmission line, comprising:

• transmitting a first signal from a driver over a first portion of the IC transmission line to an amplifier;
• transmitting a first inverted signal from the amplifier to a receiver;
• and
• after transmitting the first active signal and the first inverted signal, preparing to transmit a second signal from the driver, including:
• isolating both the first portion and the second portion of the IC transmission line;
• and
• electrically connecting the first portion of the IC transmission line to the second portion of the IC transmission line to share a stored charge between the first and second portions of the IC transmission line.

A method for sending a data signal over an integrated circuit (IC) transmission line, comprising:

• transmitting a control signal having a cycle with a predetermined active portion and a predetermined inactive portion;
• transmitting a first signal from a driver over a first portion of the IC transmission line to an amplifier during the active portion of the control signal;
• transmitting a first inverted signal from the amplifier to a receiver during the active portion of the control signal;
• and
• after transmitting the first active signal and the first inverted signal, preparing to transmit a second signal from the driver, including:
• isolating both the first portion and the second portion of the IC transmission line during the inactive portion of the control signal;
• and
• electrically connecting the first portion of the IC transmission line to the second portion of the IC transmission line to share a stored charge between the first and second portions of the IC transmission line during the inactive portion of the control signal.

A method to transmit a transmission signal over an integrated circuit transmission line that is segmented into a first integrated circuit line and a second integrated circuit line by an inverting repeater, the method comprising:

• preparing the transmission line during an inactive portion of a control signal, including:
• isolating the first integrated circuit line and the second integrated circuit line;
• and
• transferring a charge between the isolated first and second integrated circuit lines to provide a third potential on the first integrated circuit line between the first potential and the second potential;
• and
• transmitting the transmission signal during an active portion of the control signal, wherein the third potential is between a low logic potential and a high logic potential of the transmission signal.

A method for sending a data signal over an integrated circuit (IC) transmission line, comprising:

• transmitting a control signal having a cycle with a predetermined active portion and inactive portion;
• during the active portion, transmitting a first active signal from a driver through a number of inverting amplifiers on the IC transmission line to a receiver, wherein n inverting amplifiers segment the IC transmission line into n+1 segments;
• and
• during the inactive portion, isolating each of the n+1 segments of the IC transmission line, and electrically connecting each of the n+1 segments to share a stored charge among all of the n+1 segments of the IC transmission line.

A method for sending a data signal over an integrated circuit (IC) transmission line, comprising:

• transmitting a control signal having a cycle with a predetermined active portion and inactive portion;
• during the active portion, powering up a series inverting amplifiers on the IC transmission line, transmitting a first active signal from a driver through the inverting amplifiers to a receiver, wherein n inverting amplifiers segment the IC transmission line into n+1 segments;
• and
• during the inactive portion, isolating each of the n+1 segments of the IC transmission line, electrically connecting each of the n+1 segments to share a stored charge among all of the n+1 segments of the IC transmission line, and powering down each of the n inverting amplifiers.

A method of writing to an integrated circuit (IC) memory array, comprising:

• during a first portion of a period, driving a data signal corresponding to a memory address over a first segment of an IC transmission line, and driving an inverted data signal over a second segment of the IC transmission line;
• and
• during a second portion of a period, isolating the first segment and the second segment, and electrically connecting the first segment to the second segment to share a charge between the first segment and the second segment;
• and
• presenting a signal representative of the inverted data signal to the memory array.

A method of writing to an integrated circuit (IC) memory array, comprising:

• driving a data signal corresponding to a memory address over a first portion of an integrated circuit transmission line to a repeater amplifier, and an inverted data signal from the repeater amplifier over a second portion of the integrated circuit transmission line during an active portion of a cycle;
• presenting a signal representative of the inverted data signal to the memory array;
• and
• electrically isolating the first portion of the transmission line and the second portion of the transmission line, and electrically connecting the first portion of the transmission line to the second portion of the transmission line during an inactive portion of the cycle.

A method of writing to an integrated circuit (IC) memory array, comprising:

• powering up a repeater amplifier on an integrated transmission line and electrically connecting a first portion of the transmission line between a driver and the repeater amplifier and a second portion of the transmission line between the repeater amplifier and a receiver, driving a memory address data signal over a first portion of the transmission line to the repeater amplifier, and an inverted data signal over a second portion of the transmission line to the receiver during an active portion of a cycle;
• presenting a signal representative of the inverted data signal to the memory array;
• and
• electrically isolating the first portion of the transmission line and the second portion of the transmission line, shunting the isolated first portion of the transmission line to the isolated second portion of the transmission line, and powering down the repeater amplifier during an inactive portion of the cycle.

A method of writing to an integrated circuit (IC) memory array, comprising:

• transmitting a control signal having a cycle with a predetermined active portion and inactive portion;
• during the active portion, powering up a series inverting amplifiers on the IC transmission line, driving a first data signal corresponding to a memory address from a driver through the inverting amplifiers to a receiver, wherein n inverting amplifiers segment the IC transmission line into n+1 segments;
• presenting a signal representative of the inverted data signal to the memory array;
• and
• during the inactive portion, isolating each of the n+1 segments of the IC transmission line, electrically connecting each of the n+1 segments to share a stored charge among all of the n+1 segments of the IC transmission line, and powering down each of the n inverting amplifiers.

A method of writing to an integrated circuit (IC) memory array, comprising:

• transmitting a control signal having a cycle with a predetermined active portion and inactive portion;
• during the active portion of the cycle,
• driving a memory address data signal over a first portion of an integrated circuit transmission line to a repeater amplifier;
• driving the inverted data signal over a second portion of the integrated circuit transmission line;
• latching a received signal representative of the inverted data signal at a receiver during the active portion of the cycle such that the receiver is able to provide an output signal representative of the memory address data signal to the memory array;
• and
• during the inactive portion of the cycle,
• electrically isolating the first portion of the transmission line and the second portion of the transmission line, wherein the first and second portions of the transmission line have a capacitance, and one of the first and second portions of the transmission line holds more charge after driving the memory address data signal over the first portion and the inverted data signal over the second portion during the active portion of the cycle;
• and
• electrically connecting the first portion of the transmission line to the second portion of the transmission line to transfer charge between the first portion and second portion of the transmission line, wherein the first portion of the transmission line is at a potential that is between a low logic potential and a high logic potential of the memory address data signal.

An integrated circuit (IC) transmission line repeater, comprising:

• means to receive a first signal on a first segment of an IC transmission line during an active portion of a control signal cycle;
• means to transmit an inverted and amplified first signal on a second segment of an IC transmission line during the active portion of the control signal cycle;
• and
• means to share charge between the first segment and the second segment during an inactive portion of the control signal cycle.

A memory device, comprising:

• means to provide a control signal having a cycle with active and inactive portions;
• means to drive a first data signal corresponding to a memory address on a first segment of an integrated circuit (IC) transmission line during the active portion of the control signal cycle;
• means to drive an amplified and inverted first data signal corresponding to the memory address on a second segment of the IC transmission line during the active portion of the control signal cycle;
• and
• means to isolate and share charge between the first segment and the second segment during the inactive portion of the control signal cycle such that the first and second segments have an approximately equal shared charge potential,
• wherein the first data signal has a low logic potential and a high logic potential, the inverted first data signal has a high logic potential and a low logic potential, the shared charge potential being between the low logic potential and the high logic potential of the first data signal, and the shared charge potential being between the high logic potential and the low logic potential of the inverted first data signal.