Input/output buffer circuit

Abstract

In an input/output buffer circuit to which input signal voltage VBUS higher than power source voltage VDD is possibly inputted to an input/output terminal BUS, a gate terminal G3 is controlled by a signal in-phase to a input/output mode switching signal CNT outputted from a buffer circuit 5, and the power source voltage VDD is applied when it is an input mode. When the input signal voltage VBUS is lower than voltage obtained by applying threshold voltage Vthp of PMOS transistor to the power source voltage VDD (VBUS<VDD+Vthp), voltage obtained by subtracting threshold voltage Vthn of NMOS transistor from the power source voltage VDD is applied to a gate terminal G1 (VG1=VDD−Vthn). On condition that Vthn>Vthp, a PMOS transistor P1 gets conductive, whereby the power source voltage VDD is applied to a gate terminal G2 and PMOS transistor P2 is turned off. Thereby, an unnecessary current path is not formed. There is thus provided an input/output buffer circuit wherein unnecessary current does not flow in the input/output terminal BUS.

Dependencies are inferred from the claim text.