Method and apparatus for performing a hazard-free multi-bit comparsion
AssigneeSun Microsystems, Inc.
InventorThomas L. Meneghini
Life of this patent
Estimating the term…
Abstract
An exclusive OR (XOR) circuit is provided to perform a logical XOR function on multiple bits that eliminates the XOR function hazard. The XOR circuit performs a logical XOR function on data values that have been encoded to prevent the XOR function hazard from occurring.
Claims23
A logic circuit to perform an exclusive or (XOR) logic function without the logic circuit entering an unstable state comprising:
- an input circuit to convert a plurality of static input signals to a plurality of complimentary dual-rail domino output signals having one or more valid states;
- and
- an output circuit to perform a plurality of said XOR logic functions on said plurality of complimentary dual-rail domino output signals without the logic circuit entering the unstable state.
A method for performing a near simultaneous comparison of multiple bits using a logical XOR function in a manner that avoids an XOR function hazard of the logical XOR function, said method comprising the steps of:
- generating a plurality of dual-rail domino signal pairs from a plurality of input signals in a manner that avoids an unstable state in a logical XOR circuit to avoid the XOR function hazard in the logical XOR circuit;
- and
- performing the logical XOR function on the plurality of said dual-rail domino signal pairs in the logical XOR circuit to perform the near simultaneous comparison of bits without the logical XOR circuit entering the unstable state.
A circuit to perform a substantially simultaneous comparison of multiple bits, comprising:
- an encoder circuit to receive a plurality of input signals and generate a plurality of dual-rail domino output signals from the plurality of input signals in a manner that prevents of each of said plurality of dual-rail domino output signals from entering an invalid state;
- and
- an exclusive OR (XOR) logic circuit not subject to an XOR function hazard to perform the substantially simultaneous comparison of multiple bits in the plurality of dual-rail domino output signals from said encoder circuit.
An XOR logic circuit to compare multiple bits comprising,
- an encoder circuit to encode a plurality of input values asserted on a plurality of input nodes of said encoder circuit into a plurality of output value pairs;
- and
- an output circuit to perform a logical XOR function on the plurality of output value pairs to perform the comparison of the multiple bits, wherein each of the plurality of output value pairs each have three states to allow said XOR logic circuit to operate without an XOR function hazard when comparing the multiple bits.
Dependencies are inferred from the claim text.