Semiconductor integrated circuit having a gate array structure
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsYutaka Uneme, Hideaki Nagasawa
Life of this patent
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Abstract
In the semiconductor integrated circuit of a gate array structure, within a cell, a plurality of isolation transistors are disposed in series between an intra-cell gate output terminal and an intra-cell power supply wiring section, or between the intra-cell gate output terminal and an intra-cell ground wiring section. While between cells, a plurality of isolation transistors are disposed in series between an extra-cell gate output terminal and an extra-cell power supply wiring section, or between the extra-cell gate output terminal and an extra-cell ground wiring section.
Claims12
A semiconductor integrated circuit of gate array structure, comprising:
- an output section of an intra-cell gate;
- an intra-cell power supply wiring section;
- and
- a plurality of isolation transistors disposed in series between the intra-cell gate output section and the intra-cell power supply wiring section.
A semiconductor integrated circuit of gate array structure, comprising:
- an intra-cell gate output section;
- an intra-cell ground wiring section;
- and
- a plurality of isolation transistors disposed in series between the intra-cell gate output section and the intra-cell ground wiring section.
A semiconductor integrated circuit of gate array structure, comprising:
- an intra-cell gate output section;
- an intra-cell first power supply wiring section;
- a plurality of first isolation transistors disposed in series between the intra-cell gate output section and the intra-cell first power supply wiring section;
- an intra-cell second power supply wiring section;
- and
- a plurality of second isolation transistors disposed in series between the intra-cell gate output section and the intra-cell second power supply wiring section.
A semiconductor integrated circuit of gate array structure, comprising:
- an output section of an extra-cell gate;
- an extra-cell power supply wiring section in an adjacent cell;
- and
- a plurality of isolation transistors disposed in series between the extra-cell gate output section and the extra-cell power supply wiring section in the adjacent cell.
A semiconductor integrated circuit of gate array structure, comprising:
- an extra-cell gate output section;
- an extra-cell ground wiring section in an adjacent cell;
- and
- a plurality of isolation transistors disposed in series between the extra-cell gate output section and the extra-cell ground wiring section in the adjacent cell.
A semiconductor integrated circuit of gate array structure, comprising:
- an extra-cell gate output section;
- an extra-cell first power supply wiring section in an adjacent cell;
- a plurality of first isolation transistors disposed in series between the extra-cell gate output section and the extra-cell first power supply wiring section in the adjacent cell;
- an extra-cell second power supply wiring section in the adjacent cell;
- and
- a plurality of second isolation transistors disposed in series between the extra-cell gate output section and the extra-cell second power supply wiring section in the adjacent cell.
Dependencies are inferred from the claim text.