Parallel integrated circuit test apparatus and test method
AssigneeTexas Instruments Incorporated
InventorStephen M. Watts
Life of this patent
Estimating the term…
Abstract
A test apparatus (300) comprising a single handler (304) is coupled to a first tester (336) and second tester (308). A first test procedure is performed on a set of second IC's using the first tester (336), simultaneously while a second test procedure is performed on a first set of IC's using the second tester (308). Sets of IC's are tested sequentially, in parallel, by a plurality of testers (336/308) within a single handler (304).
Claims20
An apparatus for testing at least one first integrated circuit (IC) and at least one second IC, comprising:
- a first tester adapted to test the at least one first IC with a first test procedure;
- a second tester adapted to test the at least one first IC with a second test procedure simultaneously while the first tester tests the at least one second IC with the first test procedure;
- and
- a single handler coupled to the first and second testers;
- wherein the first and second test procedures are adapted to test at least some different IC parameters.
A method of testing at least one first integrated circuit (IC) and at least one second IC in an apparatus comprising a first tester and a second tester coupled to a single handler, the method comprising:
- testing the first IC with a first test procedure using the first tester;
- and
- testing the second IC with the first test procedure simultaneously while testing the first IC's with a second test procedure using the second tester, wherein testing IC's with the first test procedure comprises testing at least some different IC parameters than testing IC's with the second test procedure.
A method of testing integrated circuits (IC's), comprising:
- providing at least one first IC;
- providing at least one second IC;
- testing the at least one first IC with a first test procedure;
- and
- testing the at least one first IC with a second test procedure simultaneously while testing the at least one second IC with the first test procedure, wherein the first and second test procedures are performed within a single enclosed handler, wherein testing IC's with the first test procedure comprises testing at least some different IC parameters than testing IC's with the second test procedure.
Dependencies are inferred from the claim text.