Parallel integrated circuit test apparatus and test method
AssigneeTexas Instruments Incorporated
InventorMark A. Burns
Life of this patent
Estimating the term…
Abstract
A test apparatus (400) comprising a single handler (404) is coupled to a first tester (436) and second tester (408), wherein the first (436) and second (408) testers are coupled together. A first test procedure is performed on a set of second IC's using the first tester (436), simultaneously while a second test procedure is performed on a first set of IC's using the second tester (408). Sets of IC's may be tested in parallel by a plurality of testers (436/408) within a single handler (404). The first (436) and second (408) testers may be coupled to a multiplexer (460) to allow the use of a single test head (478), which avoids having to make contact to the integrated circuit more than once, which is particularly advantageous in wafer probe testing.
Claims33
An apparatus for testing at least one first integrated circuit (IC) and at least one second IC, comprising:
- a first tester adapted to test the at least one first IC with a first test procedure;
- a second tester adapted to test the at least one first IC with a second test procedure simultaneously while the first tester tests the at least one second IC with the first test procedure, wherein the first and second test procedures are adapted to test at least some different IC parameters, wherein the first tester is coupled to the second tester;
- and
- a single handler coupled to the first and second testers.
An apparatus for testing at least one first integrated circuit (IC) and at least one second IC, comprising:
- a first tester adapted to test the at least one first IC with a first test procedure;
- a second tester adapted to test the at least one first IC with a second test procedure simultaneously while the first tester tests the at least one second IC with the first test procedure;
- a single handler coupled to the first and second testers;
- wherein the first and second test procedures are adapted to test at least some different IC parameters;
- a first environmental chamber coupled to the first tester;
- and
- a second environmental chamber coupled to the second tester, wherein the first and second test procedures comprise subjecting the first and second IC's to different environmental tests.
An apparatus for testing at least one first integrated circuit (IC) and at least one second IC, comprising:
- a first tester adapted to test the at least one first IC with a first test procedure;
- a second tester adapted to test the at least one first IC with a second test procedure simultaneously while the first tester tests the at least one second IC with the first test procedure;
- and
- a single handler coupled to the first and second testers, wherein the first and second test procedures are adapted to test at least some different IC parameters, and wherein the first tester is integral to the handler.
A method of testing at least one first integrated circuit (IC) and at least one second IC in an apparatus comprising a first tester and a second tester coupled to a single handler, the method comprising:
- coupling the first tester to the second tester;
- testing the first IC with a first test procedure using the first tester;
- and
- testing the second IC with the first test procedure simultaneously while testing the first IC's with a second test procedure using the second tester, wherein testing IC's with the first test procedure comprises testing at least some different IC parameters than testing IC's with the second test procedure.
Dependencies are inferred from the claim text.