Digital clock detection
OwnerStephen Paul Andrew, Jonathan Francis Everedinventors
Life of this patent
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Abstract
A digital clock detector for detecting whether a digital clock, for providing an output alternating between a high value and a low value, is running or stopped, comprises: two or more digital delay gates connected to said clock, said delay gates being connected in a chain; and logic circuitry arranged to determine whether the logic levels on either side of each of said gates are the same or different, and to thereby provide an output which indicates whether said digital clock is running, or whether said digital clock has stopped while providing an output which corresponds to either said high value or said low value.
Claims20
A digital clock detector for detecting whether a digital clock, for providing an output alternating between a high value and a low value, is running or stopped, the detector comprising:
- two or more digital delay gates connected to said clock, said delay gates being connected in a chain;
- and
- logic circuitry arranged to determine whether the logic levels on either side of each of said gates are the same or different, and to thereby provide an output which indicates whether said digital clock is running, or whether said digital clock has stopped while providing an output which corresponds to either said high value or said low value.
A method of detecting whether a digital clock, for providing an output alternating between a high value and a low value, is running or stopped, the method comprising:
- delaying the digital clock signal by one or more multiples of a delay period, using one or more digital delay gates;
- determining the logic level after each delay;
- and
- determining whether said logic levels are the same or different, so as to thereby determine whether said digital clock is running, or whether said digital clock has stopped while providing an output which corresponds to either said high value or said low value.
Dependencies are inferred from the claim text.