Multi-substrate microelectronic packages and methods for manufacture

A method for packaging microelectronic substrates, comprising:

• positioning a first microelectronic substrate proximate to a second microelectronic substrate, the first microelectronic substrate having a first surface with a first connection site and further having a second surface facing opposite the first surface, the second microelectronic substrate having a first surface with a second connection site and further having a second surface facing opposite the first surface;
• coupling the first microelectronic substrate to the second microelectronic substrate to form a substrate assembly with the first surface of the first microelectronic substrate facing toward the second surface of the second microelectronic substrate;
• and
• electrically connecting the first and second connection sites by disposing a conductive material on the substrate assembly between the first and second connection sites and conforming the conductive material at least generally to a contour of the substrate assembly immediately adjacent to the conductive material.

A method for packaging microelectronic substrates, comprising:

• positioning a plurality of unsingulated first microelectronic substrates proximate to a corresponding plurality of singulated second microelectronic substrates while the first microelectronic substrates are connected to each other to form at least a portion of a microelectronic wafer, wherein each first microelectronic substrate has a first surface with a first connection site and further has a second surface facing opposite the first surface, and each second microelectronic substrate has a first surface with a second connection site and further has a second surface facing opposite the first surface;
• attaching each second microelectronic substrate to a corresponding one of the plurality of first microelectronic substrates to form a plurality of substrate assemblies with the first surface of each first microelectronic substrate facing in at least approximately the same direction as the first surface of the corresponding second microelectronic substrate, and with the second surface of each second microelectronic substrate facing toward the first surface of the corresponding first microelectronic substrate;
• and
• for each substrate assembly, electrically connecting the first connection site of the first microelectronic substrate to the second connection site of the corresponding second microelectronic substrate with a conductive structure.

A method for packaging microelectronic substrates, comprising:

• positioning a plurality of unsingulated first microelectronic substrates proximate to a corresponding plurality of singulated second microelectronic substrates while the first microelectronic substrates are connected to each other to form at least a portion of a microelectronic wafer, wherein each first microelectronic substrate has a first surface with a first connection site and further has a second surface facing opposite the first surface, and each second microelectronic substrate has a first surface with a second connection site and further has a second surface facing opposite the first surface;
• attaching each second microelectronic substrate to a corresponding one of the plurality of first microelectronic substrates to form a plurality of substrate assemblies with the first surface of each first microelectronic substrate facing in at least approximately the same direction as the first surface of the corresponding second microelectronic substrate, and with the second surface of each second microelectronic substrate facing toward the first surface of the corresponding first microelectronic substrate, and with the first and second connection sites facing in at least approximately the same direction;
• and
• for each substrate assembly, electrically connecting the first connection site of the first microelectronic substrate to the second connection site of the corresponding second microelectronic substrate by sequentially disposing at least first and second portions of a conductive material on the substrate assembly to build up a conforming elongated conductive structure connected between the first and second connection sites, at least a portion of the conductive structure conforming at least generally to a contour of the substrate assembly.

A method for packaging microelectronic substrates, comprising:

• positioning a first microelectronic substrate proximate to a second microelectronic substrate, the first microelectronic substrate having a first surface with a first connection site and further having a second surface facing opposite the first surface, the second microelectronic substrate having a first surface with a second connection site and further having a second surface facing opposite the first surface;
• coupling the first and second microelectronic substrates to form a stacked substrate assembly with the first surface of the first microelectronic substrate facing toward the second surface of the second microelectronic substrate;
• connecting the first connection site to the second connection site with a conductive connector;
• and
• providing the assembly for connecting to other microelectronic devices while a planform area of the assembly in a plane generally parallel to the second surface of the first microelectronic substrate has a size and shape at least approximately identical to that of the second surface of the first microelectronic substrate.

A method for packaging microelectronic substrates, comprising:

• positioning a first microelectronic substrate proximate to a second microelectronic substrate while the first microelectronic substrate forms at least a portion of a microelectronic wafer, the first microelectronic substrate having a first surface with a first connection site and further having a second surface facing opposite the first surface, the second microelectronic substrate having a first surface with a second connection site and further having a second surface facing opposite the first surface;
• coupling the first and second microelectronic substrates to form a stacked substrate assembly with the first surface of the first microelectronic substrate facing toward the second surface of the second microelectronic substrate;
• connecting the first connection site to the second connection site with a conductive connector;
• singulating the first microelectronic substrate from other first microelectronic substrates of the microelectronic wafer after connecting the first connection site to the second connection site;
• and
• electrically connecting the substrate assembly to other microelectronic devices while edges of the first microelectronic substrate between the first and second surfaces of the first microelectronic substrate remain exposed.

A microelectronic device package, comprising:

• a first microelectronic substrate having a first surface with a first connection site and further having a second surface facing opposite the first surface;
• a second microelectronic substrate having a first surface with a second connection site and further having a second surface facing opposite the first surface, the second microelectronic substrate being coupled to the first microelectronic substrate to form a substrate assembly with the second surface of the second microelectronic substrate facing toward the first surface of the first microelectronic substrate;
• and
• a conformal conductive link coupled between the first and second connection sites, the conductive link conforming at least generally to a contour of the substrate assembly immediately adjacent to the conformal conductive link.

A microelectronic device package, comprising:

• a first microelectronic substrate having a first surface with a first connection site and further having a second surface facing opposite the first surface;
• a second microelectronic substrate having a first surface with a second connection site and further having a second surface facing opposite the first surface, the second microelectronic substrate being coupled to the first microelectronic substrate with the second surface of the second microelectronic substrate facing toward the first surface of the first microelectronic substrate;
• and
• a conductive link coupled between the first and second microelectronic substrates, the conductive link including a first portion of a conductive material disposed on at least one of the first and second connection sites, the conductive link further including a second portion of a conductive material sequentially disposed on the first portion to link the first connection site to the second connection site.

A microelectronic device assembly, comprising:

• a wafer having a plurality of non-singulated first microelectronic substrates, each first microelectronic substrate having a first surface with a first connection site and further having a second surface facing opposite the first surface;
• a plurality of second microelectronic substrates each having a first surface with a second connection site and further having a second surface facing opposite the first surface, the second microelectronic substrates being coupled to the first microelectronic substrates while the first microelectronic substrates are non-singulated, and wherein the first surface of each first microelectronic substrate faces toward the second surface of a corresponding one of the plurality of second microelectronic substrates;
• and
• a conductive link connected between the first and second connection sites.

A microelectronic device package, comprising:

• a first microelectronic substrate having a first surface with a first connection site and further having a second surface facing opposite the first surface;
• a second microelectronic substrate having a first surface with a second connection site and further having a second surface facing opposite the first surface, the first microelectronic substrate being attached to the second microelectronic substrate with the first surface of the first microelectronic substrate facing the second surface of the second microelectronic substrate and the first and second connection sites facing in at least approximately the same direction to define a microelectronic device assembly, wherein a planform area of the assembly in a plane generally parallel to the second surface of the first microelectronic substrate has a size and shape at least approximately identical to that of the second surface;
• and
• a conductive link between the first and second connection sites.

An electronic device, comprising:

• a housing;
• and
• a microelectronic device package positioned within the housing, the microelectronic device package including:
• a first microelectronic substrate having a first surface with a first connection site and further having a second surface facing opposite the first surface;
• a second microelectronic substrate having a first surface with a second connection site and further having a second surface facing opposite the first surface, the second microelectronic substrate being coupled to the first microelectronic substrate to form a substrate assembly with the second surface of the second microelectronic substrate facing toward the first surface of the first microelectronic substrate;
• and
• a conformal conductive link coupled between the first and second connection sites, the conductive link conforming at least generally to a contour of the substrate assembly.