US 2003/0116836 A1Published application

Semiconductor package with enhanced electrical and thermal performance and method for fabricating the same

AssigneeSiliconware Precision Industries Co., Ltd.

InventorsChien-Ping Huang, Chih-Ming Huang

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Abstract

A BGA (ball grid array) package with enhanced electrical and thermal performance, and a method for fabricating the BGA package, are proposed. This BGA package is characterized by the use of a power-connecting heat spreader and a ground-connecting heat spreader, which are respectively used to electrically connect power pad and ground pad to a packaged chip as well as to dissipate heat generated by the chip during operation. The ground-connecting heat spreader is arranged to entirely cover the chip, and thereby provides good shielding effect for the chip, which helps improve electrical performance of the chip during operation. Further, the ground-connecting heat spreader is partly exposed to outside of an encapsulation body that encapsulates the chip, by which satisfactory heat-dissipation efficiency can be achieved.

Claims20

Dependent claims

A semiconductor package with enhanced electrical and thermal performance, comprising:

a substrate having a front surface and a back surface opposed to the front surface, wherein a plurality of I/O (input/output) vias, power vias and ground vias are formed to extend from the front surface to the back surface of the substrate;
at least a chip having an active surface and an inactive surface opposed to the active surface, wherein the active surface is formed with a plurality of I/O pads, power pads and ground pads, allowing the I/O pads to be electrically connected to the I/O vias of the substrate, and the active surface is further formed with a power plane and a ground plane in a manner that, the power plane is electrically connected to the power pads, and the ground plane is electrically connected to the ground pads;
and wherein the inactive surface of the chip is mounted on the front surface of the substrate;
a power-connecting heat spreader mounted over the front surface of the substrate in a manner that, the power-connecting heat spreader entirely covers the chip, and is adapted to be electrically bonded to the power vias of the substrate and the power plane on the chip;
a ground-connecting heat spreader mounted over the front surface of the substrate to entirely cover the chip in a manner that, the ground-connecting heat spreader is positioned in elevation above the power-connecting heat spreader, and adapted to be electrically bonded to the ground vias of the substrate and the ground plane on the chip;
an encapsulation body for encapsulating the front surface of the substrate, the chip, the power-connecting heat spreader and the ground-connecting heat spreader;
and
a plurality of solder balls implanted on the back surface of the substrate and electrically bonded to the vias.

5 more elements

A semiconductor package with enhanced electrical and thermal performance, comprising:

a substrate having a front surface and a back surface opposed to the front surface, wherein a plurality of I/O (input/output) vias, power vias and ground vias are formed to extend from the front surface to the back surface of the substrate;
at least a chip having an active surface and an inactive surface opposed to the active surface, wherein the active surface is formed with a plurality of I/O pads, power pads and ground pads, allowing the I/O pads to be electrically connected to the I/O vias of the substrate, and the active surface is further formed with a power plane and a ground plane in a manner that, the power plane is electrically connected to the power pads, and the ground plane is electrically connected to the ground pads;
and wherein the inactive surface of the chip is mounted on the front surface of the substrate;
a power-connecting heat spreader having a support portion, an overhead portion supported on the support portion, and a downward-extending portion protruding downwardly from the overhead portion, wherein the support portion is electrically bonded to the power vias of the substrate, and the downward-extending portion is electrically bonded to the power plane on the chip, allowing the overhead portion to be elevated in position above the chip by the support portion and the downward-extending portion in a manner that, the power-connecting heat spreader entirely covers the chip;
a ground-connecting heat spreader having a support portion, an overhead portion supported on the support portion, and a downward-extending portion protruding downwardly from the overhead portion, wherein the support portion is electrically bonded to the ground vias of the substrate, and the downward-extending portion is electrically bonded to the ground plane on the chip, allowing the overhead portion to be elevated by the support portion and the downward-extending portion in position above the overhead portion of the power-connecting heat spreader in a manner that, the ground-connecting heat spreader entirely covers the chip;
an encapsulation body for encapsulating the front surface of the substrate, the chip, the power-connecting heat spreader and the ground-connecting heat spreader, wherein the overhead portion of the ground-connecting heat spreader is exposed to outside of the encapsulation body;
and
a plurality of solder balls implanted on the back surface of the substrate and electrically bonded to the vias.

5 more elements

A method for fabricating a semiconductor package, comprising the step of:

preparing a substrate having a front surface and a back surface opposed to the front surface, wherein a plurality of I/O (input/output) vias, power vias and ground vias are formed to extend from the front surface to the back surface of the substrate;
mounting at least a chip having an active surface and an inactive surface opposed to the active surface, wherein the active surface is formed with a plurality of I/O pads, power pads and ground pads, and further formed with a power plane and a ground plane in a manner that, the power plane is electrically connected to the power pads, and the ground plane is electrically connected to the ground pads;
and wherein the inactive surface of the chip is mounted on the front surface of the substrate;
forming a plurality of bonding wires for electrically connecting the I/O pads on the chip to the I/O vias of the substrate;
mounting a power-connecting heat spreader over the front surface of the substrate;
the power-connecting heat spreader having a support portion, an overhead portion supported on the support portion, and a downward-extending portion protruding downwardly from the overhead portion, wherein the support portion is electrically bonded to the power vias of the substrate, and the downward-extending portion is electrically bonded to the power plane on the chip, allowing the overhead portion to be elevated in position above the chip by the support portion and the downward-extending portion in a manner that, the power-connecting heat spreader entirely covers the chip;
mounting a ground-connecting heat spreader over the front surface of the substrate;
the ground-connecting heat spreader having a support portion, an overhead portion supported on the support portion, and a downward-extending portion protruding downwardly from the overhead portion, wherein the support portion is electrically bonded to the ground vias of the substrate, and the downward-extending portion is electrically bonded to the ground plane on the chip, allowing the overhead portion to be elevated by the support portion and the downward-extending portion in position above the overhead portion of the power-connecting heat spreader in a manner that, the ground-connecting heat spreader entirely covers the chip;
forming an encapsulation body for encapsulating the front surface of the substrate, the chip, the power-connecting heat spreader and the ground-connecting heat spreader;
and
implanting a plurality of solder balls on the back surface of the substrate, and electrically bonding the solder balls to the vias.

8 more elements

Dependencies are inferred from the claim text.