Programmable impedance control circuit

A programmable impedance control circuit using an M times internal impedance for an N times external impedance (N≠M), comprising:

• a pull-up circuit comprising a MOS array being supplied with a first voltage, an external resistance having an N times external impedance, a pad outputting a second voltage obtained in combination of the first MOS array and the external resistance, a first reference generator for combination of the first MOS array and the external resistance, a first reference generator for generating a first reference voltage corresponding to N/(N+M) times of the first voltage as a first reference voltage for the second voltage outputted from the pad, a first comparator for comparing the second voltage with the first reference voltage to output an impedance in compliance the first reference voltage for the second voltage, and a first counter for generating a signal corresponding to the impedance outputted from the first comparator to output it to an up-driver and up-terminator and at the same time feeding back it to the first MOS array;
• and
• a pull-down circuit comprising a second MOS array being supplied with a first voltage and receiving a signal outputted from the first counter to control an impedance, a third MOS array connected to the second MOS array at one terminal and connected to ground at the other terminal, a second comparator for comparing the third voltage obtained by combination of the second MOS array and the third MOS array with the second reference voltage that is a half of the first voltage to output an impedance in compliance the second reference voltage for the third voltage, and a second counter for generating a signal corresponding to the impedance outputted from the second comparator to output it to a down-driver and down-terminator and at the same time feeding back it to the third MOS array.

A programmable impedance control circuit using an M times internal impedance for an N times external impedance (N≠M), comprising:

• a pull-up circuit comprising a PMOS current source being supplied with a first voltage or second voltage, an external resistance having an N times external impedance, a pad outputting a third voltage obtained in combination of the PMOS current source and the external resistance, a first reference generator for generating a fourth reference voltage corresponding to N/(N+M) times of the first voltage as a first reference voltage for the third voltage outputted from the pad, a first comparator for comparing the third voltage with the fourth voltage that is the first reference voltage to output an impedance in compliance the first reference voltage for the third voltage as an current to output it and at the same time feeding back it to the PMOS, a current mirror for copying the current from the first comparator, a second comparator for comparing the output voltage from the current mirror with the second reference voltage that is a half of the first voltage to output it, and a first counter for generating a signal corresponding to the impedance outputted from the second comparator to output it to an up-driver and up-terminator and at the same time feeding back it to the first MOS array;
• and
• a pull-down circuit comprising a second MOS array being supplied with a first voltage, an NMOS array connected to the second MOS array at one terminal and connected to ground at the other terminal, a third comparator for comparing the fifth voltage obtained by combination of the second MOS array and the NMOS array with the second reference voltage to output an impedance in compliance the second reference voltage for the fifth voltage, and a second counter for generating a signal corresponding to the impedance outputted from the third comparator to output it to a down-driver and down-terminator and at the same time feeding it back to the second MOS array.

A programmable impedance control circuit, comprising:

• a voltage divider, comprising:
• MOS array supplied with a first voltage;
• and
• an external resistance having an external impedance equal to N times said external resistance;
• said voltage divider outputting a second voltage;
• a reference voltage generator adapted to generate a third voltage corresponding to N/(N+M) times said first voltage as a reference voltage for said second voltage;
• and
• wherein M times internal impedance is used for N times external impedance (N=M or N≠M).