Semiconductor device, semiconductor gate array, electro-optical device, and electronic equipment

A semiconductor gate array, comprising:

• a supporting substrate having insulation at least at a surface thereof;
• a semiconductor layer formed on the surface of the supporting substrate;
• a plurality of MOS transistors formed in the semiconductor layer, each of the MOS transistors comprising a channel region of a first conductive type formed on the surface of the supporting substrate, a source region and a drain region of a second conductive type formed on the surface of the supporting substrate so as to sandwich the channel region, an insulating layer formed on the channel region, and an electrode formed on the insulating layer;
• a first semiconductor region provided on the surface of the supporting substrate at least at one end in a channel width direction of at least one of the source region and the drain region along a channel length direction;
• and
• a second semiconductor region of the first conductive type provided on the surface of the supporting substrate so as to sandwich the first semiconductor region by the source region or the drain region along the first semiconductor region, the second semiconductor region having an impurity concentration which is higher than that in the channel region, and the first semiconductor region having an impurity concentration which is lower than that in the source region and the drain region and is lower than that in the second semiconductor region.

A semiconductor device, comprising:

• a supporting substrate having insulation at least at a surface thereof;
• a semiconductor layer formed on the surface of the supporting substrate;
• a plurality of MOS transistors formed in the semiconductor layer and connected to each other in series, each of the MOS transistors comprising a channel region of a first conductive type formed on the surface of the supporting substrate, a source region and a drain region of a second conductive type formed on the surface of the supporting substrate so as to sandwich the channel region, an insulating layer formed on the channel region, and an electrode formed on the insulating layer;
• a first semiconductor region provided on the surface of the supporting substrate at least at one end in a channel width direction of one of source region and the drain region among source regions and drain regions of respective MOS transistors along a channel length direction, which is not directly connected to an electrical power source;
• a second semiconductor region of the first conductive type provided on the surface of the supporting substrate so as to sandwich the first semiconductor region by the source region or the drain region along the first semiconductor region;
• and
• a third semiconductor region of the first conductive type provided on the surface of the supporting substrate at least at one end in the channel width direction of one of the source region and the drain region along the source region and the drain region, which is directly connected to the electrical power source,
• each of the second semiconductor region and the third semiconductor region having an impurity concentration which is higher than that in the channel region, and
• the first semiconductor region having an impurity concentration which is lower than that in the source region and the drain region and is lower than that in the second semiconductor region.