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US 2003/0116763 A1Published application
Semiconductor integrated circuit device
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsAkira Yamazaki, Takeshi Fujino, Atsuo Mangyo
Life of this patent
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Abstract
A comparator compares a predetermined number of data bits with respective expected value data bits. A select circuit selects either of an output signal of this comparator and the predetermined number of data bits in accordance with an operation mode instructing signal for transference to test output nodes. A test of a logic merged memory is executed continuously to a space column space and a normal column space of the memory.
Claims10
A semiconductor integrated circuit device comprising:
- test data output nodes arranged in a width of a plurality of bits;
- an internal data bus, greater in bit width than said test data output nodes, for transferring internal data;
- and
- test circuitry for comparing a predetermined number of bits of the internal data on said internal data bus with bits of test expected value data equal in bit width to said test data output nodes for each bit, and outputting data indicating respective comparison results to said test data output nodes in parallel.
1 more element
Dependencies are inferred from the claim text.