US 2003/0116439 A1Published application

Method for forming encapsulated metal interconnect structures in semiconductor integrated circuit devices

AssigneeInternational Business Machines Corporation

InventorsSoon-Chen Seo, Carlos J. Sambucetti, Xiaomeng Chen, Zheng Chen, Vincent McGahay, Daniel C. Edelstein

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Abstract

An advanced back-end-of-line (BEOL) integration scheme for semiconductor devices using very low-k dielectric materials is disclosed. The disclosed method for forming a metal interconnect structure in a semiconductor integrated circuit device comprises forming the metal interconnects using a through-mask plating (TMP) process, and encapsulating the interconnects with a barrier layer by selectively depositing a barrier layer material using an electroless liner plating process or by non-selectively depositing a blanket insulator diffusion barrier layer using PVD or CVD techniques.

Claims20

Dependent claims

A method for forming a metal interconnect in an integrated circuit device, the method comprising the steps of:

(a) depositing a metal seed layer onto a partially fabricated integrated circuit device;
(b) depositing a photoresist layer onto the metal seed layer;
(c) forming an opening in the photoresist layer by a photolithography process, thereby exposing a portion of the metal seed layer;
(d) depositing metal in the opening by a plating process;
(e) removing the photoresist layer and metal seed layer, thereby exposing the partially fabricated integrated circuit device;
(f) depositing a conformal barrier layer onto the metal;
and
(g) depositing a dielectric material onto the partially fabricated integrated circuit device.

5 more elements

Dependencies are inferred from the claim text.