Method and system for predicting worst-case capacitive and inductive switching vector
AssigneeIntel Corporation
InventorMark Elzinga
Life of this patent
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Abstract
A method and system for determination of the worst case switching vector, which greatly reduces the search space complexity. A single simulation is performed in the time-domain wherein the roles of the victim and attacker conductors are switched. In particular, the search space is reduced by virtue of the fact that certain combinations for the behavior attacker conductors are excluded. Only the phases of the attacker signals need to be determined.
Claims18
A method for determining a worst case switching vector in a circuit network, wherein the circuit network is represented as including a victim node and a plurality of attacker nodes, comprising:
- (a) setting the victim node to function as an attacker node and the attacker nodes to function as victim nodes;
- (b) applying a test signal to the victim node;
- (c) determining a response signal Ni[t] for each attacker node generated by the application of the test signal to the victim node;
- (d) determining a time instant associated with a maximum noise;
- and,
- (e) determining a phase for each response signal at the time instant of maximum noise.
A system for determining a worst case switching vector in a circuit network, wherein the circuit network is represented as including a victim node and a plurality of attacker nodes, comprising:
- a central processing unit (“CPU”), wherein the CPU is adapted to:
- set the victim node to function as an attacker node and the attacker nodes to function as victim nodes;
- apply a test signal to the victim node;
- determine a response signal Ni[t] for each attacker node generated by the application of the test signal to the victim node;
- determine a time instant associated with a maximum noise;
- and, determine a phase for each response signal at the time instant of maximum noise.
A program storage device storing instructions executable by a CPU including instructions for determining a worst case switching vector in a circuit network, wherein the circuit network is represented as including a victim node and a plurality of attacker nodes, comprising instructions for:
- setting the victim node to function as an attacker node and the attacker nodes to function as victim nodes;
- applying a test signal to the victim node;
- determining a response signal Ni[t] for each attacker node generated by the application of the test signal to the victim node;
- determining a time instant associated with a maximum noise;
- and,
- determining a phase for each response signal at the time instant of maximum noise.
Dependencies are inferred from the claim text.