Semiconductor memory device capable of failure analysis with system in operation

Abstract

In accordance with a voltage impressed to NC pins 1 and 2 unused by the system of interest a debug mode control circuit activates a reference voltage generation circuit, a data input/output circuit, an internal signal monitor circuit and a signal history record and output circuit selectively in a debug mode. When activated in the debug mode, the reference voltage generation circuit sets an internal power supply voltage to have a level of an external power supply voltage to internally supply power. The data input/output circuit reduces an ability to drive outputting data. The internal signal monitor circuit monitors any internal signal, and the signal history record and output circuit records a history in variation of any internal signal and outputs it to the debug mode control circuit. Thus there can be provided a semiconductor memory device capable of failure analysis without affecting the system operation.

Dependencies are inferred from the claim text.