Restartable logic bist controller

A built-in self-test circuit to test logic within an integrated circuit, comprising:

• means for applying a sequence of test patterns to the logic in a test of the integrated circuit, wherein the sequence of test patterns comprises at least a first test pattern and a last test pattern;
• and
• means for generating a signature based on results of applying test patterns in the sequence of test patterns to the logic;
• means for suspending signature generation while receiving the results of applying the test patterns.

A method of testing core logic within an integrated circuit, comprising:

• generating a sequence of test patterns, wherein the sequence comprises at least a first and last test pattern;
• applying test patterns in the sequence to scan chains within the core logic, wherein test responses are generated in response to the applying;
• shifting the test responses to a scan monitor comprising a signature generation element, the signature generation element having a state, wherein the state changes in response to the test responses;
• and
• suspending changes in the state of the signature generation element during the shifting of the test responses to the scan monitor and prior to obtaining a final state of the signature generation element.

A method for testing an integrated circuit comprising testing circuitry and core logic circuitry, the method comprising:

• applying a sequence of test patterns to the core logic circuitry;
• receiving test pattern response values in a signature generator, wherein the test pattern response values are responsive to the application of the sequence of test patterns to the core logic circuitry;
• and
• temporarily suspending signature generation in the signature generator at any desired point in the sequence of test patterns so that one or more test patterns or portions of test patterns are not used in the signature generation.

A method of testing core logic within an integrated circuit using a built-in self-test circuit, comprising:

• applying a sequence of test patterns to scan chains within the core logic, wherein test responses are generated in response to the applying, and wherein the sequence comprises at least a first test pattern and a last test pattern;
• shifting the test responses to a scan monitor comprising a signature generation element;
• suspending signature generation in the signature generation element prior to obtaining a final signature for the sequence;
• obtaining an intermediate signature from the signature generation element;
• performing a comparison of the intermediate signature with a known good signature;
• and
• responsive to the comparison, repeating the acts of applying, shifting, suspending, obtaining and performing a comparison for a subsequence of the sequence.