Scan clock circuit and method therefor

A method of scan testing a target circuit having at least one clock domain comprising:

• receiving a reference clock;
• providing a shift/capture clock signal to the target circuit, the shift/capture clock signal being in phase with the reference clock;
• and
• providing a launch clock signal for scan testing having a phase relationship relative to the shift/capture clock signal such that when a period of the launch clock signal is followed by the shift/capture clock signal, a pulse-to-pulse delay between the launch clock signal and the shift/capture clock signal is equal to a nominal clock period of the at least one clock domain to permit scan test launching and capturing in a domain-specific at-speed period much shorter than a period of the reference clock.

A scan clock circuit comprising:

• a clock generator for receiving a reference clock having a first frequency and providing a high frequency operating clock having a second frequency that is higher than the first frequency;
• a global storage device coupled to the clock generator for receiving the high frequency operating clock, the global storage device storing a sequence of state values;
• a first local storage device for storing a phase control signal;
• clock waveform generation circuitry having a first input coupled to the global storage device for receiving the sequence of state values, a second input coupled to the first local storage device for receiving the phase control signal, a control input for receiving a test control signal, and an output for providing a scan test clock having the first frequency, the scan test clock generating shift and capture cycles having a pulse of predetermined phase and duration when the test control signal is negated and generating a launch cycle of the scan test clock when the test control signal is asserted and having a pulse of differing phase that creates a pulse-to-pulse delay between the launch cycle and an immediately following capture cycle that is equal to a nominal clock period of a predetermined clock domain to permit scan test launching and capturing in a domain-specific at-speed period much shorter than a period of the reference clock;
• and
• output logic circuitry coupled to the high frequency operating clock and to the clock waveform generation circuitry, the output logic circuitry providing a divided version of the high frequency clock during a normal mode of operation and providing the scan test clock during a test mode of operation.