Parallel testing system for semiconductor memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsHyuk Kwon, Jeong-Ho Bang, Hyun-Seop Shim, Yong-Woon Kim, Hyoung-Young Lee, Young-Gu Shin
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Abstract
A testing system for memory Devices Under Test (DUTs) uses an improved wiring scheme to increase the parallel test number. In a preferred embodiment, the parallel testing system increases the parallel test number by commonly connecting data input/output pins of the memory devices to an input/output channel of the testing system. Driving channels may also be connected in parallel to driving pins of the plurality of semiconductor memory devices under test.
Claims20
A parallel testing system for testing a plurality of semiconductor memory devices having a plurality of data input/output pins, said system comprising:
- a test board comprising a data input/output channel;
- and
- said input/output channel being connected in parallel to data input/output pins of a plurality of semiconductor memory devices under test.
A parallel testing system for testing semiconductor memory devices having a plurality of data input/output pins, said testing system comprising:
- a test board having a plurality of data input/output channels connected in parallel to data input/output pins of a plurality of semiconductor memory devices under test;
- and
- a clock configured to select the semiconductor memory devices under test, wherein a selected one of the devices under test produces an output signal based on a test signal of the testing system.
A method for testing semiconductor memory devices, said method comprising:
- commonly connecting a plurality of input/output pins of the semiconductor memory device to an input/output channel of a testing system.
Dependencies are inferred from the claim text.