System for enhancing fault tolerance and security of a computing system
AssigneeKoninklijke Philips Electronics N.V.
InventorsJudson A. Lehman, Rajeev Sethia
Life of this patent
Estimating the term…
Abstract
A system for enhancing fault tolerances and security of a computing system having a system clock through monitoring the computing system for at least one of a series of security attacks and upon detection of security attacks, switching the system from the system clock to a secure clock.
Claims19
A method for enhancing the security of a system operating in conjunction with a clock signal from a system clock, comprising:
- monitoring the system for detecting a fault in the system;
- upon detection of a fault, switching the system from operating in conjunction with a clock signal from the system clock to operate in conjunction with a secure clock signal from a secure clock.
An apparatus for enhancing the security of a system operating in conjunction with a clock signal from a system clock, the apparatus comprising:
- a secure clock generating a secure clock signal;
- a clock monitor circuit configured to monitor the system for detecting a fault;
- clock switching circuitry, the clock switching circuitry operably coupled to the clock monitor circuit, the system clock signal and the secure clock signal;
- the clock switching circuitry configured, upon the detection of a fault, to switch the system from operating in conjunction with a clock signal from the system clock to operate in conjunction with a secure clock signal from a secure clock.
An application specific integrated circuit comprising:
- a processor;
- a clock generating a system clock signal for operation of the processor;
- the secure clock further generating a secure clock signal;
- a clock monitor circuit configured to monitor the application specific integrated circuit for detecting a fault;
- clock switching circuitry, the clock switching circuitry operably coupled to the clock monitor circuit, the system clock signal and the secure clock signal;
- the clock switching circuitry configured, upon the detection of a fault, to switch the processor from operating in conjunction with a system clock signal to operating in conjunction with the secure clock signal.
Dependencies are inferred from the claim text.