Method and apparatus for optimizing clock distribution to reduce the effect of power supply noise

A circuit on a die for optimization of clock delay to minimize the effect of power supply noise comprising:

• a clock generator;
• a clock tree comprising a plurality of clock nets;
• at least one delay element connected between the clock generator and the clock tree, the at least one delay element delaying a clock signal from the clock generator to the clock tree;
• and
• at least two storage devices, the at least two storage devices storing data received upon receipt of the clock signal,
• wherein the delay caused by the at least one delay element is set to provide a delay of the clock signal that minimizes the effect of noise from a power source on the clock signal as it travels along the clock nets and on the data as it travels along a data path between two of the at least two storage devices.

A circuit on a die for optimization of clock delay to minimize the effect of power supply noise comprising:

• a clock generator;
• a clock tree comprising a plurality of clock nets;
• at least two storage devices, the at least two storage devices storing data received upon receipt of a clock signal from the clock generator;
• and
• at least one filter element connected between a power source and at least one element transferring the clock signal in the plurality of clock nets, the at least one filter element filtering noise from the power source.

A processor microcircuit comprising:

• a clock generator;
• a clock tree comprising a plurality of clock nets;
• at least one delay element connected between the clock generator and the clock tree, the at least one delay element delaying a clock signal from the clock generator to the clock tree;
• and
• at least two storage devices, the at least two storage devices storing data received upon receipt of the clock signal,
• wherein the delay caused by the at least one delay element is set to provide a delay of the clock signal that minimizes the effect of noise from a power source on the clock signal as it travels along the clock nets and on the data as it travels along a data path between two of the at least two storage devices.

A method for optimizing clock distribution in a circuit to reduce the effect of power supply noise comprising:

• determining a transient curve for a power supply voltage droop, a delay and sensitivity of a pre-distribution, a delay and sensitivity of a clock distribution for a clock signal, and a delay and sensitivity of a data path, the clock signal comprising a plurality of clock pulses;
• deriving normalized sensitivity curves for the pre-distribution, the clock distribution, and the data path;
• computing the delay error due to propagation of generation clock edge through the pre-distribution and the clock distribution by integrating the normalized sensitivity curve for pre-distribution and the normalized sensitivity curve for the clock distribution for each clock pulse;
• computing the delay modulation for the data path by integrating the normalized sensitivity curve for the data path at a first clock pulse, the first clock pulse representing when the power supply voltage droop begins;
• computing the delay error due to propagation of sampling clock edge through the pre-distribution and the clock distribution by integrating the normalized sensitivity curve for the pre-distribution and the normalized sensitivity curve for the clock distribution;
• computing the net timing loss for the first clock pulse by summing the integrals resulting from the first computing step, the second computing step, and the third computing step;
• and
• repeating all computing steps for each successive clock pulse until a desired number of clock pulses have been completed.