Countermeasure method for a microcontroller based on a pipeline architecture
AssigneeGemplus
InventorNathalie Feyt
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Abstract
The present invention relates to a countermeasure method for a microcontroller able to execute sequences of instructions (INSn), the said instructions being executed according to a so-called pipeline method, characterised in that the method consists in randomly introducing at least one waiting time (B) between two consecutive instructions (INSn, INSn+1) and/or within at least one instruction (INSn). The method according to the invention is implemented by the electronics of the microcontroller rather than by software addition.
Claims11
A countermeasure method for a microcontroller able to execute sequences of instructions (INSn), the said instructions being executed according to a so-called pipeline method, characterised in that the method consists in randomly introducing at least one waiting time (B) between two consecutive instructions (INSn, INSn+1) and/or within at least one instruction (INSn).
A countermeasure method according to any one of the preceding claims, characterised in that the waiting time (B) is introduced randomly several times during the execution of the sequence of instructions.
A countermeasure method according to any one of the preceding claims, characterised in that the waiting time (B) is introduced following a logic command preceding the sequence of instructions to be protected.
A countermeasure method according to any one of the preceding claims, characterised in that it is effected through a non-software implementation which is the direct responsibility of the microcontroller instructions decoding electronics.
A countermeasure method according to any one of the preceding claims, characterised in that the introduction of the waiting time (B) is adjusted statically or dynamically, by means of an electronic or software parameter, so as to adjust the variability of the execution of one and the same sequence of instructions.
A method according to any one of the preceding claims, characterised in that it is implemented in an integrated circuit chip having a microcontroller with RISC architecture with pipeline.
Dependencies are inferred from the claim text.