System and method for effectively implementing isochronous processor cache
AssigneesSony Corporation, Sony Electronics Inc.
InventorsGlen D. Stone, Scott D. Smyers, Bruce A. Fairman
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Abstract
A system and method for effectively implementing isochronous processor cache comprises a memory device for storing high-priority isochronous information, an isochronous cache coupled to the memory device for locally caching the isochronous information from the memory device, and a processor device for accessing and utilizing the isochronous information that is stored in the isochronous cache. The isochronous cache is reserved for storing the isochronous information, and may be reconfigured into a selectable number of cache channels of varying size that each corresponds to an associated isochronous process.
Claims22
A system for optimizing processor operations, comprising:
- a transmission source configured to provide priority information for use by an electronic device;
- a cache memory coupled to said transmission source and configured for temporarily storing said priority information, said cache memory including an isochronous cache that is reserved for storing only said isochronous data on a priority basis, said cache memory also including an asynchronous cache that is configured to store asynchronous data on a non-priority basis;
- and
- a processor coupled to said cache memory for utilizing said priority information from said cache memory.
A method for optimizing processor operations, comprising the steps of:
- providing priority information from a transmission source for use by an electronic device;
- configuring a cache memory to store said priority information, said cache memory including an isochronous cache that is reserved for storing only said isochronous data on a priority basis, said cache memory also including an asynchronous cache that is configured to store asynchronous data on a non-priority basis;
- and
- accessing said priority information from said cache memory by using a processor.
A computer-readable medium comprising program instructions for optimizing processor operations by performing the steps of:
- providing priority information from a transmission source for use by an electronic device;
- configuring a cache memory to store said priority information, said cache memory including an isochronous cache that is reserved for storing only said isochronous data on a priority basis, said cache memory also including an asynchronous cache that is configured to store asynchronous data on a non-priority basis;
- and
- accessing said priority information from said cache memory by using a processor.
A system for optimizing processor operations, comprising:
- means for providing priority information from a transmission source for use by an electronic device;
- means for configuring a cache memory to store said priority information, said cache memory including an isochronous cache that is reserved for storing only said isochronous data on a priority basis, said cache memory also including an asynchronous cache that is configured to store asynchronous data on a non-priority basis;
- and
- means for accessing said priority information from said cache memory by using a processor.
Dependencies are inferred from the claim text.