Data driven power management
AssigneeIntel Corporation
InventorsAndre Zaccarin, Trevor Pering, Marco Y. Wirasinghe
Life of this patent
Estimating the term…
Abstract
A power management system for digital circuityr uses data buffer monitoring to determine appropriate processor clock speed or voltage. This allows a processor to be switched from a low power state to a high power state when a monitored data buffer level feeding data to a power intensive application is greater than a second memory buffer level. The processor is switched from a high power state to a low power state when the monitored data buffer level is less than a first memory buffer level.
Claims21
A method comprising:
- determining a first memory buffer level for at least one memory buffer providing data to digital circuitry,
- determining a second memory buffer level for a memory buffer, the second memory buffer level being set greater than the first memory buffer level,
- monitoring data buffer levels in memory, and
- switching digital circuitry from a first state to a second state when the monitored data buffer level is greater than the second memory buffer level, and switching the digital circuitry from a second state to a first state when the monitored data buffer level is less than the first memory buffer level.
An article comprising a computer-readable medium which stores computer-executable instructions, the instructions defined to cause a computer to:
- determine a first memory buffer level for at least one memory buffer providing data to digital circuitry,
- determine a second memory buffer level for a memory buffer, the second memory buffer level being set greater than the first memory buffer level,
- monitor data buffer levels in memory, and
- switch digital circuitry from a first state to a second state when the monitored data buffer level is greater than the second memory buffer level, and switch the digital circuitry from a second state to a first state when the monitored data buffer level is less than the first memory buffer level.
A power reduction system comprising:
- a memory buffer monitoring unit to determine a first and second memory buffer level for at least one memory buffer providing data to digital circuitry, with the second memory buffer level being set greater than the first memory buffer level, and
- a switching unit to adjust digital circuitry state, moving from a first state to a second state when monitored data buffer level in the memory buffer monitoring unit is greater than the second memory buffer level, and moving from a second state to a first state when monitored data buffer level is less than the first memory buffer level.
Dependencies are inferred from the claim text.