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US 2003/0115426 A1Published application
Congestion management for high speed queuing
AssigneeIntel Corporation
InventorsMark B. Rosenbluth, Debra Bernstein, Gilbert Wolrich
Life of this patent
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Abstract
A device such a network device implemented as a hardware-based multi-threaded processor is described. The processor can execute a computer instruction that is a write queue descriptor count instruction that causes the instruction sequence to write a single word containing a queue count for each of a number of queue entries in a queue array cache.
Claims14
A computer instruction comprises:
- a write queue descriptor count instruction that causes a processor to write a single word containing a queue count for each of a plurality of queue entries in a queue array cache.
A method comprising:
- in a processor, maintaining a count field for queue descriptors of active output queues current in a memory.
Apparatus comprising:
- a memory containing queue descriptors representing output queues, a queue manager programming engine and a content addressable memory (CAM);
- a processor connected to the memory, the processor containing a memory controller, the memory controller having a cache containing a queue descriptor array for storing a subset of the queue descriptors;
- and
- an array in memory for storing a count of queue descriptors in the subset.
1 more element
A computer program product residing on a computer readable medium having instructions stored thereon which, when executed by the processor, cause the processor to:
- maintain a count field for queue descriptors of active output queues current in a memory.
Dependencies are inferred from the claim text.