Semiconductor memory device and electronic apparatus

An electronic apparatus comprising:

• a semiconductor memory device performing a refresh operation for retaining data and outputting a busy signal during the refresh operation;
• and
• a controller controlling said semiconductor memory device,
• wherein said controller does not access said semiconductor memory device when the busy signal is outputted from said semiconductor memory device.

An electronic apparatus comprising:

• a semiconductor memory device performing a refresh operation for retaining data and outputting a busy signal during the refresh operation;
• and
• a controller controlling said semiconductor memory device,
• wherein said controller outputs a same command repeatedly when the busy signal is outputted from said semiconductor memory device.

An electronic apparatus comprising:

• a semiconductor memory device performing a refresh operation for retaining data, outputting a busy signal during the refresh operation and having a refresh counter outputting refresh addresses during the refresh operation;
• and
• a controller controlling said semiconductor memory device and having a counter corresponding to said refresh counter,
• wherein said controller causes said counter to operate when the busy signal is outputted from said semiconductor memory device.

A semiconductor memory device, comprising:

• memory blocks, each comprising memory cells;
• and
• word lines provided for selecting said memory cells,
• wherein, while the memory cells selected by the word line are being refreshed, said device accepts a command sent for the memory block including said word line, interrupts a refresh operation of said memory cells selected by said word line, executes the command, and, then, restarts the refresh operation of said memory cells selected by said word line.

A semiconductor memory device, comprising an automatic reading portion which comprises:

• an address counter which generates an address for automatically reading data from said device when automatic reading is externally instructed to perform;
• and
• an access-accepting allowing/rejecting signal receiving portion which receives an access-accepting allowing/rejecting signal output from a data transfer destination and indicating whether or not said destination agrees to accept access,
• wherein said automatic reading portion automatically reads out data from said device when the access-accepting allowing/rejecting signal indicates that said destination agrees to accept access.

An electronic apparatus comprising:

• a first semiconductor memory device comprising an automatic reading portion which comprises:
• an address counter which generates an address for automatically reading data from said device when automatic reading is externally instructed to perform;
• and
• an access-accepting allowing/rejecting signal receiving portion which receives an access-accepting allowing/rejecting signal output from a destination indicating whether or not said destination allows access,
• wherein said automatic reading portion automatically reads data from said device when the access-accepting allowing/rejecting signal indicates that said destination allows access;
• and
• a second semiconductor memory device comprising:
• an automatic writing portion which, when automatic writing is externally instructed to perform, automatically writing data to said device in internally generated addresses;
• and
• an automatic writing indicating signal outputting portion which outputs an automatic writing indicating signal, which indicates that automatic writing is being performed, during the automatic writing operation.