Multiprocessor system

Abstract

A multiprocessor system is described including a plurality of processors. At least one level of cache memory is operatively connected to each of the processors. At least one memory unit is shared by at least two of the processors. A status memory, in correspondence to each processor, is configured to store a current status in correspondence to memory regions capable of being stored in the cache memories. The current status indicates whether a memory region is non-shared. The system includes logic, in correspondence to and operatively connected to each processor, for generating minimum cache-coherence activities in response to a memory access request by a respective processor. The logic includes first cache-coherent minimizing logic that is configured to generate a direct memory access request for one of a next level of cache memory and the shared memory unit in response to a memory access request by the respective processor to a memory region causing a cache-miss and indicated as non-shared by the current status.

Dependencies are inferred from the claim text.