Method of hot switching data transfer rate on bus
AssigneeVIA Technologies, Inc.
InventorsChau-Chad Tsai, Chi-Che Tsai, Chih-Kuo Kao
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Abstract
The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.
Claims11
A method of hot switching data transfer rate on the bus, to dynamically switch the bus data transfer rate between a first control chip and a second control chip, comprising the steps of:
- the first control chip and the second control chip receiving a transfer rate switching command;
- when either there is no data transaction processed or the data transaction process is finished, the first control chip issuing a bus release connect command;
- the first control chip and the second control chip entering into the bus release connect state according to the bus release connect command;
- either the first control chip or the second control chip issuing a bus re-connect command;
- and the first control chip and the second control chip re-connecting to the changed data transfer rate according to the transfer rate switching command.
A method of hot switching data transfer rate on the bus, comprising the steps of:
- a bus between a first control chip and a second control chip receiving a transfer rate switching signal before data transfer is interrupted;
- and when the first control chip and the second control chip are re-connecting, providing one of a plurality of data transfer rates to the bus according to the transfer rate switching signal.
A method of hot switching data transfer rate on the bus, to dynamically switch a plurality of data transfer rates on a bus between a first control chip and a second control chip, comprising the steps of:
- the first control chip and the second control chip receiving a data transfer rate switching command, and temporarily storing the data transfer rate switching command into a transfer rate register of the first control chip and the second control chip;
- when either there is no data transaction processed or the data transaction process is finished, issuing a bus release connect command to have the first control chip and the second control chip enter into a bus release connect state;
- and when either the first control chip or the second control chip issues a bus re-connect command, the first control chip and the second control chip switching to one of the data transfer rates on the bus according to the content of the transfer rate register.
Dependencies are inferred from the claim text.