Output data path capable of multiple data rates
AssigneeMicron Technology, Inc.
InventorsJohn D. Porter, William N. Thompson, Larren Gene Weber
Life of this patent
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Abstract
Systems, data paths and methods of transferring data. By utilizing the systems, data paths, and methods, data can be transferred at a single or double rate. One embodiment of the present invention provides a system having a data unit, an output register, and a holding register. The output register is coupled to the data unit. The holding register is coupled to the data unit and the output register. Data from the data unit is passed to the output register and the holding register substantially simultaneously and data from the holding register is then passed to the output register. Data can be output from the output register.
Claims45
A device comprising:
- a data unit;
- an output register connected to the data unit;
- a holding register connected to the data unit and the output register;
- and
- a rate select logic connected to the output register and the holding register for selecting a data rate of data outputted from the output register.
A device comprising:
- a data unit including memory cells;
- an output register connected to the data unit;
- a holding register connected to the data unit and the output register;
- and
- a rate select logic connected to the output register and the holding register for selecting a data rate of data outputted from the output register, wherein the rate select logic is configured to select the data rate between a first data rate and a second data rate unequal to the first data rate.
A device comprising:
- a data unit;
- an output register connected to the data unit for receiving data from the data unit;
- a holding register connected to the data unit and the output register for receiving data from the data unit and for transferring data to the output register;
- and
- a rate select logic connected to the output register and the holding register for selecting a data rate of data outputted from the output register, wherein the rate select logic is configured to select the data rate between a single data rate and a double data rate, wherein a rate of the double data rate is twice a rate of the single data rate.
A system comprising:
- a processor;
- a data unit including memory cells;
- a holding register connected to the memory cells;
- an output register connected to the holding register and the processor for outputting data from the memory cells;
- and
- a rate select logic connected to the output register and the holding register for selecting a data rate of data outputted from the output register.
A method comprising:
- selecting a data rate of data outputted from an output register;
- receiving at the output register a first piece of data from a data unit;
- outputting the first piece of data from the output register;
- receiving at a holding register a second piece of data from the data unit;
- transferring the second piece of data from the holding register to the output register;
- and
- outputting the second piece of data from the output register.
A method comprising:
- transferring two pieces of data from a memory array, in which a first piece of data of the two pieces of data is transferred to an output register and a second piece of data of the two pieces of data is transferred to a holding register;
- outputting the first piece of data from the output register to a data pin;
- transferring the second piece of data from the holding register to the output register;
- outputting the second piece of data from the output register to the data pin;
- and
- selecting a data rate of data outputted at the data pin.
A method comprising:
- selecting a data rate of data outputted from a data pin;
- passing a first piece of data from a memory array to an output register at a first edge of a clock signal;
- outputting the first piece of data from the output register to the data pin;
- passing a second piece of data from the memory array to a holding register at the first edge of the clock signal;
- passing the second piece of data from the holding register to the output register at a second edge of the clock signal;
- and
- outputting the second piece of data from the output register to the data pin.
Dependencies are inferred from the claim text.