Look-ahead carry adder circuit
AssigneeIntel Corporation
InventorThomas D. Fletcher
Life of this patent
Estimating the term…
Abstract
A look-ahead carry adder circuit has multiple stages that are grouped into a carry generation blocks. The size of one of the carry generation blocks is three stages. There may be other carry generation blocks that are of a size that is a whole number multiple of three stages. In an embodiment, the look-ahead carry adder has only one critical path. In a further embodiment, the load on the critical path is minimized by using buffers.
Claims25
An apparatus comprising a look-ahead carry adder circuit having a plurality of stages that are grouped into a plurality of carry generation blocks, wherein the size of one of the carry generation blocks is three stages.
A method of adding two multi-bit addends, the method comprising:
- receiving two multi-bit addends;
- determining a propagate value and a corresponding generate value for each bit of the addends;
- determining a carry-out value for each propagate value based at least in part on the propagate value and corresponding generate value, wherein the carry-out values are determined by a plurality of carry generation blocks, and wherein one of the carry generation blocks determines exactly three of the carry-out values;
- and
- determining a sum value for each carry-out value based at least on part of the carry-out value.
A look-ahead carry adder circuit, comprising:
- inputs to receive two multi-bit addends;
- a plurality of blocks each of which is connected to one input bit of both of the multi-bit addends, wherein each block has a propagate output and a generate output;
- a plurality of carry generation blocks each having inputs connected to two or more of said propagate outputs and two or more of said generate outputs, wherein one of the carry generation blocks is connected to exactly three of the propagate outputs and three of the generate outputs, and wherein each of the carry generation blocks has a plurality of carry outputs;
- and
- a plurality of final blocks each of which is connected to one of said carry outputs and each having a sum output.
Dependencies are inferred from the claim text.