Performance optimized approach for efficient downsampling operations
AssigneeIntel Corporation
InventorsYan Hou, Hong Jiang, Kam Leung
Life of this patent
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Abstract
The present invention provides an algorithm and hardware structure for numerical operations on signals that is reconfigurable to operate in a downsampling or non-downsampling mode. According to one embodiment, a plurality of adders and multipliers are reconfigurable via a switching fabric to operate as a plurality of MAAC kernels (described in detail below), when operating in a non-downsampling mode and a plurality of MAAC kernels and AMAAC kernels (described in detail below), when operating in a downsampling mode.
Claims18
A reconfigurable hardware apparatus for performing computational operations in one of a downsampling mode and a non-downsampling mode, comprising:
- a plurality of adders, each of the plurality of adders including at least two inputs and one output;
- a plurality of multipliers, each of the plurality of multipliers including at least two inputs and one output;
- a switching fabric for switching between a downsampling mode of operation and a non-downsampling mode of operation, wherein the switching fabric provides for a configuration of the inputs and outputs of the adders with respect to the inputs and outputs of the multipliers;
- and,
- a control logic block for controlling the switching fabric.
A hardware apparatus for computing an IDCT in one of a downsampling mode and a non-downsampling mode comprising:
- a data loader block;
- a plurality of MAAC kernels;
- and
- at least one AMAAC kernel.
A system for performing downsampling computations:
- at least one AMAAC kernel, wherein each AMAAC kernel includes:
- a multiplier block;
- a first adder block;
- a second adder block;
- a register block;
- wherein the first adder block receives two inputs (e(i) and a(i)) and an output of the first adder block is coupled to a first input of the multiplier block, the multiplier block receiving a second input (b(i)) and an output of the multiplier block coupled to a first input of the second adder block, the second adder block receiving a second input (c(i)) and an output of the second adder block is coupled to an input of the register block, an output of the register block coupled to a third input of the second adder block;
- at least one MAAC kernel, wherein each MAAC kernel includes:
- a multiplier block;
- an adder block;
- a register block;
- wherein an output of the multiplier block is coupled to a first input of the adder block, an output of the adder block is coupled to an input of the register block and an output of the register block is coupled to a second input of the adder block, the adder block receiving a third input.
A digital signal processor wherein the digital signal processor includes:
- at least one MAAC kernel;
- and,
- at least one AMAAC kernel.
Dependencies are inferred from the claim text.