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AssigneeCadence Design Systems, Inc.
InventorsPawan Kulshreshtha, Robert J. Palermo, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin
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A high accuracy method for transistor-level static timing analysis is disclosed. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor-level circuit simulator allows efficient invocation of the simulation.
A method for transistor-level static timing analysis using embedded simulation, comprising the steps of:
A method for calculating delays of a circuit, comprising the steps of:
A system for transistor-level timing analysis using embedded simulation, comprising:
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