Method and apparatus for generating a data pattern for simultaneously testing multiple bus widths

A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method that facilitates generating a bus testing data pattern for simultaneously testing multiple bus widths, the method comprising:

• receiving a list of bus widths to be tested;
• receiving a root test pattern, wherein a width of the root test pattern equals a smallest bus width in the list of bus widths;
• creating a second test pattern by inverting each bit of the root test pattern and concatenating this inverted root pattern with the root test pattern;
• creating a third test pattern by repeating the second test pattern zero or more times so that third test pattern width equals a next larger bus width in the list of bus widths;
• and
• creating a fourth test pattern by inverting each bit of the third test pattern and concatenating this inverted third test pattern with the third test pattern;
• whereby the fourth test pattern can be used to simultaneously test the smallest bus width and the next larger bus width in the list of bus widths.

An apparatus that facilitates generating a bus testing data pattern for simultaneously testing multiple bus widths, the apparatus comprising:

• a receiving mechanism that is configured to receive a list of bus widths to be tested;
• wherein the receiving mechanism is further configured to receive a root test pattern, and wherein a width of the root test pattern equals a smallest bus width in the list of bus widths;
• a pattern creating mechanism that is configured to create a second test pattern by inverting each bit of the root test pattern and concatenating this inverted root pattern with the root test pattern;
• wherein the pattern creating mechanism is further configured to create a third test pattern by repeating the second test pattern zero or more times so that third test pattern width equals a next larger bus width in the list of bus widths;
• and
• wherein the pattern creating mechanism is further configured to create a fourth test pattern by inverting each bit of the third test pattern and concatenating this inverted third test pattern with the third test pattern;
• whereby the fourth test pattern can be used to simultaneously test the smallest bus width and the next larger bus width in the list of bus widths.