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US 2003/0113991 A1Published application
Semiconductor device manufacturing method
AssigneeKabushiki Kaisha Shinkawa
InventorTooru Maeda
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Abstract
A wire bonding method in which conductive patterns that are electrically connected at one end to pads are formed on the surface of a wafer on which a plurality of pads have been formed, and bumps used as connecting points located on the other ends of the conductive patterns are connected to the connecting terminals of a substrate. A disposition of bumps that differs from the disposition of the pads is obtained by the conductive patterns, thus eliminating and adjusting mismatching between the disposition of the pads and the disposition of the connecting terminals.
Claims14
A semiconductor device manufacturing method comprising:
- a conductive pattern formation step that forms a plurality of conductive patterns, which are electrically connected at one ends thereof to a plurality of pads, on an integrated circuit on which said plurality of pads are formed, and
- a connecting step that connects connecting points located at other ends of said conductive patterns to a substrate;
- wherein
- a disposition of said connecting points that differs from a disposition of said pads is obtained by means of said conductive patterns.
1 more element
Dependencies are inferred from the claim text.