Method of fabricating a MOS transistor with a shallow junction
OwnerKent Kuohua Changinventor
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Abstract
A semiconductor wafer is provided having both a memory array area and a periphery circuit region defined on the surface of the semiconductor wafer. A gate composed of a silicon oxide layer and a silicon germanium layer is formed on the surface of the periphery circuit region, and a spacer, a source and a drain of the MOS transistor are formed around the gate. Finally, a nickel (Ni) layer is formed on the surface of the source and the drain, and a rapid thermal annealing process (RTA process) with a temperature ranging between 400° C. and 500° C. is performed for forming a silicon nickel layer on the surface of the source and the drain. Additionally, a shallow junction for the source and the drain is formed.
Claims17
A method of forming a metal-oxide semiconductor (MOS) transistor with a shallow junction in nitride read only memory (NROM), the method comprising:
- providing a semiconductor wafer with both a memory array area and a periphery circuit region defined on a surface of a substrate of the semiconductor wafer;
- forming a silicon oxide layer on the surface of the periphery circuit region;
- forming a silicon germanium layer on the surface of the silicon oxide layer;
- patterning the silicon germanium layer to form a gate of the MOS transistor on the surface of the substrate;
- forming a spacer around the gate;
- forming a source and a drain of the MOS transistor in the substrate;
- forming a nickel (Ni) layer on the surface of the source and the drain;
- and
- performing a rapid thermal annealing process (RTA process) to react the nickel layer with the surface of the source and the drain to form a silicon nickel layer.
A method of forming a metal-oxide semiconductor (MOS) transistor with a shallow junction, the method comprising:
- providing a semiconductor wafer;
- forming a silicon oxide layer on a silicon substrate of the semiconductor wafer;
- performing an in-situ doped chemical vapor deposition (CVD) process for forming a silicon germanium layer on the surface of the silicon oxide layer;
- patterning the silicon germanium layer to form a gate of the MOS transistor on the surface of the silicon substrate;
- forming a spacer around the gate;
- performing a first ion implantation process to form two doping areas on the silicon substrate adjacent to two related sides of the gate;
- performing a thermal annealing process to drive dopants into the two doping areas to form a source and a drain of the MOS transistor;
- forming a nickel (Ni) layer on the surface of the source and the drain;
- and
- performing a rapid thermal annealing process (RTA process) to react the nickel layer with the surface of the source and the drain to form a silicon nickel layer on the surface of the source and the drain.
Dependencies are inferred from the claim text.