Implanted asymmetric doped polysilicon gate FinFET
AssigneeInternational Business Machines Corporation
InventorsDavid M. Fried, Edward J. Nowak, Jed H. Rankin
Life of this patent
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Abstract
An asymmetric field effect transistor (FET) that has a threshold voltage that is compatible with current CMOS circuit designs and a low-resistance gate electrode is provided. Specifically, the asymmetric FET includes a p-type gate portion and an n-type gate portion on a vertical semiconductor body; an interconnect between the p-type gate portion and the n-type gate portion; and a planarizing structure above the interconnect.
Claims28
A method of forming a plurality of conductive structures on a substrate comprising the steps of:
- forming a first semiconductor structure of a first conductivity type, a second semiconductor structure of a second conductivity type, and a third semiconductor structure on a substrate, said third semiconductor structure being disposed between said first and second semiconductor structures and being separated therefrom by an insulator structure;
- depositing an interconnect layer over at least said first, second and third semiconductor structures;
- forming a planarizing conductor on said interconnect layer, said planarizing conductor having etch characteristics similar to those of said interconnect layer and said first and second semiconductor structures, but different from those of said insulator structure;
- and
- patterning and etching said planarizing conductor, said interconnect layer, and said first and second semiconductor structures so that each has at least one lateral dimension that is substantially the same.
An asymmetric field effect transistor (FET) comprising:
- a p-type gate portion and an n-type gate portion on a vertical semiconductor body;
- an interconnect between said p-type gate portion and said n-type gate portion;
- and
- a planarizing structure above said interconnect.
An asymmetric field effect transistor (FET) comprising:
- a p-type gate portion and an n-type gate portion on a vertical single crystal Si semiconductor body, said p-type and n-type gate portions are composed of polysilicon;
- a metal silicide interconnect between said p-type gate portion and said n-type gate portion;
- and
- a planarizing doped polysilicon layer above said interconnect.
Dependencies are inferred from the claim text.