Semiconductor device and manufacturing method thereof
AssigneesHitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
InventorsMasatada Horiuchi, Takashi Takahama
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Abstract
A high performance super-minituarized double gate SOIMOS being fabricated by re-distributing the impurity with high concentration at the interface of a buried gate insulative film and by aligning the double gate in a self-aligned manner and furthermore, by isolating completely the buried gate electrodes electrically from each other, in which a multi-layered SOI substrate having an amorphous or polycrystal semiconductor layer constituted by way of a buried gate insulative film to a lower portion of an SOI layer is used, ion implantation is applied to the semiconductor layer in a pattern opposite to the upper gate electrode and the buried gate is constituted in a self-alignment relation with the upper gate.
Claims19
A method of manufacturing a semiconductor integrated circuit device comprising the steps of:
- preparing a wafer in which a first semiconductor layer comprising an amorphous semiconductor or polycrystal semiconductor, a first insulative film and a second semiconductor area are stacked in this order,
- forming a second insulative film to a partial region on the main surface of the second semiconductor layer of the wafer including a region to be formed a gate electrode,
- forming an impurity layer at high concentration to a region in the first semiconductor layer opposing to the region to be formed the gate electrode,
- forming a third insulative film on the second semiconductor layer to the region to be formed the gate electrode and
- disposing an upper gate electrode to the region to form the gate electrode above the main surface of the second semiconductor layer on contact with the third insulative film.
A method of manufacturing a semiconductor integrated circuit device comprising the steps of:
- preparing a wafer comprising a first semiconductor layer, a second insulative film and a second semiconductor layer;
- wherein said first semiconductor layer, said second insulative film, and said second semiconductor layer formed on a support substrate in this order,
- forming a third insulative film on the main surface of the second semiconductor layer,
- depositing an ion implantation stopper film on the third insulative film,
- disposing an opening to the ion implantation stopper film corresponding to a region to be formed the gate electrode,
- penetrating desired impurity ions in the opening through the third insulative film, the second semiconductor film and the second insulative film thereby forming an impurity diffusion layer comprising impurity at high concentration in the first semiconductor layer, and
- disposing an upper gate electrode above the main surface of the wafer so as to oppose the impurity diffusion layer.
A method of manufacturing a semiconductor integrated circuit device comprising the steps of:
- preparing a wafer comprising a first semiconductor layer, a second insulative film and a second semiconductor layer;
- wherein said first semiconductor layer, said second insulative film, and said second semiconductor layer formed on a first insulative film disposed on a support substrate in this order,
- forming a third insulative film on the main surface of the second semiconductor layer,
- forming an ion implantation stopper film on the third insulative film,
- forming an opening reaching the first insulative film to a desired portion of a multi-layered film comprising the ion implantation stopper film, the third insulative film, the second semiconductor layer, the second insulative film and the first semiconductor layer,
- forming an insulation isolative film in the opening by depositing an insulative film in the opening to a thickness higher than that of the multi-layered film and polishing the insulative film to a desired thickness,
- introducing an impurity at high concentration to at least a portion of the first semiconductor layer in plural regions insulation isolated from each other by the insulation isolation film, and
- forming an upper gate electrode on the main surface of the wafer so as to oppose the introduction region of the impurity at high concentration.
A semiconductor integrated circuit device comprising:
- a first semiconductor layer comprising a polycrystal semiconductor, a second insulative film, a second semiconductor layer and a third insulative film;
- wherein said first semiconductor layer, said second insulative film, said second semiconductor layer and said third insulative film formed on said first insulative film on a support substrate;
- and
- a source region and a drain region formed at opposing positions in the second semiconductor layer and a channel portion place between the source region and the drain region, and comprising:
- an upper gate electrode disposed on contact with a third insulative layer on the second semiconductor layer corresponding to the channel portion;
- and
- an impurity diffusion layer at high concentration formed to a region opposing to the upper gate electrode in the first semiconductor layer.
Dependencies are inferred from the claim text.