US 2003/0112915 A1 · Lock detector circuit for dejitter phase lock loop (PLL)

Abstract

A phase lock loop lock detect circuit determines whether an output signal of the phase lock loop is in phase-frequency synchronization with an input reference timing signal and provides an unlock alarm signal indicating that the output signal of a phase lock loop is no longer in phase-frequency synchronization with an input reference timing signal. The lock detection circuit has a first logic function circuit to combine a frequency increase signal and a frequency decrease signal of said phase lock loop to provide a frequency deviation signal. The first logic function in the preferred embodiment of this invention is an OR gate. The output of the first logic function circuit is an input to a second logic function circuit. The second logic function circuit combines the frequency deviation signal with the input reference signal, which is applied to a second input of the second logic function, to determine that the frequency deviation signal has a greater duration than a portion of a cycle of said input reference signal and provide an unlock alarm signal. The second logic function circuit in the preferred embodiment of this invention is an AND gate. The lock detection circuit further includes a latching circuit in communication with the second logic function and the input reference signal to capture and retain said unlock alarm signal indicating loss of phase-frequency lock of said phase lock loop.

Claims56

Dependent claims

A lock detection circuit in communication with a phase lock loop to detect phase-frequency lock of an output frequency signal of said phase lock loop with an input reference signal, comprising:

a first logic function circuit to combine a frequency increase signal and a frequency decrease signal of said phase lock loop to provide a frequency deviation signal;
and
a second logic function circuit to combine the frequency deviation signal with the input reference signal to determine that the frequency deviation signal has a greater duration than a portion of a cycle of said input reference signal and provide an error signal.

A phase lock loop system comprising:

a phase-frequency detector to detect a difference in frequency between an output frequency of said phase lock loop and an input reference frequency of said phase lock loop;
and
a lock detection circuit to detect loss of phase-frequency lock of the output frequency signal of said phase lock loop with the input reference signal and upon detection of said loss of phase-frequency lock provide an unlock alarm, said lock detection circuit comprising:
a first logic function circuit to combine a frequency increase signal and a frequency decrease signal received from said phase-frequency detector to provide a frequency deviation signal;
and
a second logic function circuit to combine the frequency deviation signal with the input reference signal to determine that the frequency deviation signal has a greater duration than a portion of a cycle of said input reference signal and provide said unlock alarm.

3 more elements

A clock extraction circuit to provide an alarm indicating that a local oscillator signal is no longer in phase-frequency synchronism with an reference timing signal extracted from a data stream, said clock extraction circuit comprises:

a clock extractor to remove said timing signal from said data stream;
a phase lock loop in communication with the clock extractor to receive said timing signal and adjust a phase and frequency of the local oscillator signal synchronize said local oscillator signal to the timing signal;
and
a lock detection circuit to detect loss of phase-frequency lock of the local oscillator signal with the timing signal and upon detection of said loss of phase-frequency lock provide an unlock alarm, said lock detection circuit comprising:
a first logic function circuit to combine a frequency increase signal and a frequency decrease signal received from said phase lock loop to provide a frequency deviation signal, and
a second logic function circuit to combine the frequency deviation signal with the timing signal to determine that the frequency deviation signal has a greater duration than a portion of a cycle of said timing signal and provide said unlock alarm.

3 more elements

A synchronous communication receiver system to receive a synchronous transport signal containing data and an embedded reference timing signal and to extract said data and the reference timing signal, comprising:

a receiver to receive and buffer said synchronous transport signal;
and
a clock extraction circuit in communication with the receiver to receive the synchronous transport signal and to provide an alarm indicating that a local oscillator signal is no longer in phase-frequency synchronism with an reference timing signal extracted from a data stream, said clock extraction circuit comprises:
a clock extractor to remove said timing signal from said synchronous transport signal,
a phase lock loop in communication with the clock extractor to receive said reference timing signal and adjust a phase and frequency of the local oscillator signal synchronize said local oscillator signal to the timing signal, and
a lock detection circuit to detect loss of phase-frequency lock of the local oscillator signal with the timing signal and upon detection of said loss of phase-frequency lock provide an unlock alarm, said lock detection circuit comprising:
a first logic function circuit to combine a frequency increase signal and a frequency decrease signal received from said phase lock loop to provide a frequency deviation signal, and
a second logic function circuit to combine the frequency deviation signal with the timing signal to determine that the frequency deviation signal has a greater duration than a portion of a cycle of said timing signal and provide said unlock alarm.

5 more elements

a receiver to receive and buffer said synchronous transport signal;
and
a clock extraction circuit in communication with the receiver to receive the synchronous transport signal and to provide an alarm indicating that a local oscillator signal is no longer in phase-frequency synchronism with an reference timing signal extracted from a data stream, said clock extraction circuit comprises:
a clock extractor to remove said timing signal from said synchronous transport signal,
a phase lock loop in communication with the clock extractor to receive said reference timing signal and adjust a phase and frequency of the local oscillator signal synchronize said local oscillator signal to the timing signal, and
a lock detection circuit to detect loss of phase-frequency lock of the local oscillator signal with the timing signal and upon detection of said loss of phase-frequency lock provide an unlock alarm, said lock detection circuit comprising:
a phase-frequency detector in communication with the phase lock loop to receive the output frequency signal and the input reference signal to generate a frequency increase signal and a frequency decrease signal indicative of an amount of phase-frequency deviation of the output frequency signal has from the input reference signal,
a first logic function circuit connected to the phase frequency detector to combine a frequency increase signal and a frequency decrease signal to provide a frequency deviation signal, and
a second logic function circuit to combine the frequency deviation signal with the timing signal to determine that the frequency deviation signal has a greater duration than a portion of a cycle of said timing signal and provide said unlock alarm.

6 more elements

A synchronous communication system for the transfer of a synchronous transport signal, comprising:

a synchronous transmission apparatus to combine a data signal and a timing reference signal to form the synchronous transport signal;
and
a synchronous communication receiver apparatus in communication with the synchronous transmission apparatus to receive the synchronous transport signal band to extract said data and the reference timing signal, comprising:
a receiver to receive and buffer said synchronous transport signal,
a clock extraction circuit in communication with the receiver to receive the synchronous transport signal and to provide an alarm indicating that a local oscillator signal is no longer in phase-frequency synchronism with the reference timing signal extracted from a synchronous transport signal, said clock extraction circuit comprises:
a clock extractor to remove said timing signal from said synchronous transport signal,
a phase lock loop in communication with the clock extractor to receive said reference timing signal and adjust a phase and frequency of the local oscillator signal synchronize said local oscillator signal to the timing signal, and
a lock detection circuit to detect loss of phase-frequency lock of the local oscillator signal with the timing signal and upon detection of said loss of phase-frequency lock provide an unlock alarm, said lock detection circuit comprising:
a first logic function circuit to combine a frequency increase signal and a frequency decrease signal received from said phase lock loop to provide a frequency deviation signal, and
a second logic function circuit to combine the frequency deviation signal with the timing signal to determine that the frequency deviation signal has a greater duration than a portion of a cycle of said timing signal and provide said unlock alarm.

7 more elements

A synchronous communication system for the transfer of a synchronous transport signal, comprising:

a synchronous transmission apparatus to combine a data signal and a timing reference signal to form the synchronous transport signal;
a synchronous communication receiver apparatus in communication with the synchronous transmission apparatus to receive the synchronous transport signal band to extract said data and the reference timing signal, comprising:
a receiver to receive and buffer said synchronous transport signal,
a clock extraction circuit in communication with the receiver to receive the synchronous transport signal and to provide an alarm indicating that a local oscillator signal is no longer in phase-frequency synchronism with the reference timing signal extracted from a synchronous transport signal, said clock extraction circuit comprises:
a clock extractor to remove said timing signal from said synchronous transport signal,
a phase lock loop in communication with the clock extractor to receive said reference timing signal and adjust a phase and frequency of the local oscillator signal synchronize said local oscillator signal to the timing signal, and
a lock detection circuit to detect loss of phase-frequency lock of the local oscillator signal with the timing signal and upon detection of said loss of phase-frequency lock provide an unlock alarm, said lock detection circuit comprising:
a phase-frequency detector in communication with the phase lock loop to receive the output frequency signal and the input reference signal to generate a frequency increase signal and a frequency decrease signal indicative of an amount of phase-frequency deviation of the output frequency signal has from the input reference signal,
a first logic function circuit connected to the phase frequency detector to combine a frequency increase signal and a frequency decrease signal to provide a frequency deviation signal, and
a second logic function circuit to combine the frequency deviation signal with the timing signal to determine that the frequency deviation signal has a greater duration than a portion of a cycle of said timing signal and provide said unlock alarm.

7 more elements

Dependencies are inferred from the claim text.

Lock detector circuit for dejitter phase lock loop (PLL)

Life of this patent

Lock detector circuit for dejitter phase lock loop (PLL)

Life of this patent

Abstract

Claims56